Apparatuses and methods for shared codeword in 2-pass access operations
AssigneeMicron Technology, Inc.
InventorsSujeet Ayyapureddi, Scott E. Smith
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.
Claims20
A method comprising:
- reading a plurality of metadata bits from a memory array;
- reading a plurality of data bits and a plurality of parity bits from the memory array;
- combining the plurality of data bits and the plurality of metadata bits into a shared codeword;
- determining errors in the shared codeword based on the plurality of parity bits;
- generating a modified shared codeword by modifying the plurality of data bits based on write data bits and modifying the plurality of metadata bits based on write metadata bits;
- generating an updated plurality of parity bits based on the modified shared codeword;
- writing the modified plurality of data bits and the updated plurality of parity bits to the memory array;
- and
- writing the modified plurality of metadata bits to the memory array.
An apparatus comprising:
- at least one data terminal configured to receive write data and write metadata as part of a write operation;
- a memory array;
- an error correction code (ECC) circuit;
- and
- a shared codeword logic circuit configured combine a plurality of data bits and plurality of metadata bits from the memory array to generate a shared codeword, wherein the ECC circuit is configured to determine errors in the shared codeword based on a plurality of parity bits from the memory array to generate a corrected shared codeword, and wherein the shared codeword logic circuit is further configured to modify the corrected shared codeword based on the write data and the write metadata to generate a modified shared codeword, wherein the modified shared codeword is written to the memory array.
An apparatus comprising:
- a memory array comprising a plurality of data column planes and an extra column plane;
- an error correction code (ECC) circuit;
- and
- a column decoder, wherein responsive to a write operation the column decoder is configured to provide a first column select signal and a first read command to a selected one of the plurality of data column planes, provide a second column select signal and a second read command to each of the plurality of data column planes, provide the second column select signal and a first write command to each of the plurality of data column planes and provide the first column select signal and a second write command to the selected one of the plurality of data column planes, and
- wherein responsive to the first and the second read command the ECC circuit is configured to receive a shared codeword comprising data and metadata from the memory array and correct the shared codeword based on parity bits from the memory array and wherein responsive to the first and the second write command a modified shared codeword based on the corrected shared codeword is written to the memory array.
Dependencies are inferred from the claim text.