Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorsYoung Mok Jeong, Hong Ki Moon
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows; a scrub control circuit configured to perform an error check operation on each of the plurality of rows; and a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.
Claims21
A memory device comprising:
- a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows;
- a scrub control circuit configured to perform an error check operation on each of the plurality of rows;
- and
- a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.
A memory device comprising:
- a plurality of normal cell blocks and at least one error correction code (ECC) cell block;
- a first detection signal generation circuit configured to generate, during an error check operation, a first detection signal according to a local error signal for a first normal cell block adjacent to the at least one ECC cell block, among the plurality of normal cell blocks;
- a second detection signal generation circuit configured to generate a second detection signal according to a local error signal for the at least one ECC cell block, during the error check operation;
- a third detection signal generation circuit configured to generate, during the error check operation, a third detection signal according to a local error signal for a second normal cell block adjacent to the at least one ECC cell block, among the plurality of normal cell blocks;
- a severity determination circuit configured to generate a detection signal based on the first to third detection signals;
- an error storage circuit configured to store a row address according to the detection signal;
- and
- a write-back control circuit configured to control a write-back operation of a row corresponding to the stored row address, to be skipped.
An operating method of a memory device including a plurality of normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows, the operating method comprising:
- performing an error check operation on a target row among the plurality of rows;
- generating a detection signal based on local error signals for the normal cell blocks and the at least one ECC cell block, during the error check operation;
- storing a severe address for the target row in an error storage circuit according to the detection signal;
- initializing the detection signal when completing the error check operation,
- wherein the performing the error check operation, the generating the detection signal, the storing the severe address, and the initializing the detection signal are repeatedly performed on the plurality of rows;
- comparing the severe address stored in the error storage circuit with an input address to generate a masking signal;
- and
- performing a write-back operation during the error check operation or a read-modify-write (RMW) operation, wherein the write-back operation is skipped according to the masking signal.
Dependencies are inferred from the claim text.