System and method of checking integrity of an instruction decoder of a processing system
AssigneeNXP USA, Inc.
InventorsIani Bogdan Almajan, Joseph Charles Circello
Life of this patent
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AssigneeNXP USA, Inc.
InventorsIani Bogdan Almajan, Joseph Charles Circello
Estimating the term…
A checker pipeline for checking integrity of an instruction decoder of a primary processor pipeline of a processing system including an instruction fetch checker and an instruction decoder checker. The processor pipeline includes an instruction fetch stage that receives an instruction with fields and the instruction decoder stage that decodes the instruction into instruction field values. The instruction fetch checker receives and converts instruction correction information provided with the instruction into instruction byte parity information. The instruction decoder checker includes a parity converter that converts the instruction byte parity information and instruction field information into predicted field parity information used to check the integrity of the instruction decoder. The instruction correction information is ECC bits or the like which are converted into instruction byte parity bits. The parity converter combines instruction byte parity bits with corresponding instruction bits using a logic operation into the predicted field parity information.
A checker pipeline for checking integrity of an instruction decode stage of a primary processor pipeline of a processing system, the primary processor pipeline including an instruction fetch stage configured to receive an instruction comprising a plurality of fields and the instruction decoder stage configured to decode the instruction into a plurality of instruction field values, the checker pipeline comprising:
A method of checking integrity of an instruction decode stage of a primary processor pipeline of a processing system, the primary processor pipeline including an instruction fetch stage configured to receive an instruction comprising a plurality of fields and the instruction decoder stage configured to decode the instruction into a plurality of instruction field values, the method comprising:
A self-checking processing system, comprising:
Dependencies are inferred from the claim text.