Core test method and core test circuit
AssigneeMediaTek Singapore Pte. Ltd.
InventorsJianguo Ren, Hung-Yu Chiou, Cheng-Tien Wan, Chao-Yang Yeh, Wei-Lien Chen, Man-Yun Su, Zemin Xu, Wen-Hao Hsueh, Wei-Chuan Liu
Life of this patent
Estimating the term…
Abstract
A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).
Claims13
A core test method, for testing a processing circuit with multiple cores, comprising:
- (a) testing each of the multiple cores to determine defects, generating a first logic value when a core is determined as failed, and generating a second logic value when a core is determined as non-failed;
- (b) recording the generated logic value for each core;
- (c) performing a first performance test according to an operation frequency and performing a second performance test according to an operation voltage on all of the cores to generate performance data corresponding to each core;
- (d) generating a scan output according to the generated performance data and the generated logic value for each core;
- and
- (e) accessing the generated logic value for each core for filtering the performance data of each corresponding core.
A core test circuit for a processing circuit with multiple cores, comprising:
- a data receiving circuit, configured to receive a defect result for a defect test of each of the multiple cores to generate defect result codes for each core, or to receive performance data of a first performance test according to an operation frequency and a second performance test according to an operation voltage of the multiple cores to generate performance data codes for each core;
- a logic circuit, coupled to the data receiving circuit, configured to receive the performance data codes for each core, or configured to receive the defect result codes for each core to generate a defect result value, wherein the defect result value is a first logic value when a core is determined as failed, and the defect result value is a second logic value when a core is determined as non-failed;
- a recording unit, coupled to the logic circuit, configured to record the defect result value;
- and
- a multiplexer, coupled to the logic circuit and the data receiving circuit, configured to output a logic output in a first mode, and to output the defect result codes or the performance codes in a second mode;
- wherein in the first mode, the logic circuit generates the logic output according to the defect result value recorded in the recording unit and the performance data codes for each core, and the logic output is output by the multiplexer as a scan output, and the performance data of each core is filtered by accessing the corresponding defect result value recorded in the recording unit.
Dependencies are inferred from the claim text.