Architecture to prevent controller-to-controller deadlock
AssigneeMicrosoft Technology Licensing, LLC
InventorYaron Baruch Shapiro
Life of this patent
Estimating the term…
Abstract
An integrated circuit chip includes a secondary controller coupled to a deadlock solver that provides a communication interface to a primary controller. The deadlock solver stores control logic executable to detect a reset event indicator on a secondary controller that is indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state. Based at least in part on detection of the reset event indicator, the deadlock solver transmits a signal pattern to the secondary controller that mimics a transaction from a primary controller. The signal pattern assisting the secondary controller in exiting a reset state.
Claims20
An integrated circuit (IC) comprising:
- a deadlock solver that provides a communication interface between a primary controller and a secondary controller, the deadlock solver storing control logic executable to:
- detect a reset event indicator on the secondary controller, the reset event indicator being indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state;
- and
- based at least in part on detection of the reset event indicator, transmit a signal pattern to the secondary controller that mimics a transaction from a primary controller, the transaction including a clock signal that the secondary controller uses to reset an internal clock during a reset pattern that the secondary controller performs to exit the reset state.
A method comprising:
- detecting a reset event indicator on a secondary controller, the reset event indicator being indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state;
- and
- based at least in part on detection of the reset event indicator, transmitting a signal pattern to the secondary controller that mimics a transaction from a primary controller, the transaction including a clock signal that the secondary controller uses to reset an internal clock during a reset pattern that the secondary controller performs to exit the reset state.
A system comprising:
- first switching circuitry configured to selectably toggle a data input source of an SDA signal input to a secondary controller, the data input source being selectably toggled between an on-chip data source and an off-chip data source;
- second switching circuitry configured to selectably toggle a clock input source of a serial clock (SCL) signal to the secondary controller, the clock input source being selectably toggled between an on-chip clock and an off-chip clock;
- and
- control logic executable to detect a reset event indicator on the secondary controller and, based at least in part on the detection of the reset event indicator:
- drive the on-chip clock and the on-chip data source to transmit a signal pattern while the on-chip data source is selected as the data input source of the SDA signal and while the on-chip clock is selected as the clock input source of the SCL signal, the signal pattern mimicking a transaction from a primary controller that is effective to assist the secondary controller in exiting a reset state.
Dependencies are inferred from the claim text.