Memory aware context switching

A system for executing a plurality of software threads, comprising:

• a plurality of processing circuitries;
• a plurality of memory areas connected to the plurality of processing circuitries, each memory area associated with at least one of the plurality of processing circuitries;
• and
• at least one hardware processor, connected to the plurality of processing circuitries and configured for:
• in each of a plurality of iterations:
• while the plurality of processing circuitries executes the plurality of software threads, collecting, for each software thread of one or more of the plurality of software threads, a plurality of thread statistical values indicative of a plurality of memory accesses to at least some of the plurality of memory areas performed when executing the software thread;
• for at least one software thread of the one or more software threads, performing an analysis, comprising the plurality of thread statistical values thereof;
• and
• configuring one of the at least one processing circuitry associated with the preferred memory area to execute the at least one software thread;
• wherein the plurality of software threads each execute part of a compute kernel of a software program, where the compute kernel comprises a plurality of loop iterations for accessing application data of the software program such that each of the plurality of software threads executes some of the plurality of loop iterations, accessing at least some of the application data thereby;
• wherein the at least one hardware processor is further configured for identifying the preferred memory area by additionally or alternatively performing another analysis of a code of the plurality of software threads to identify the compute kernel and additionally or alternatively to identify the application data;
• and
• wherein performing the analysis is after executing an instruction immediately preceding the compute kernel and before executing a first instruction of the compute kernel.

A method for executing a plurality of software threads, comprising:

• in each of a plurality of iterations:
• while a plurality of processing circuitries executes the plurality of software threads, collecting, for each software thread of one or more of the plurality of software threads, a plurality of thread statistical values indicative of a plurality of memory accesses to at least some of a plurality of memory areas performed when executing the software thread, where the plurality of memory areas are connected to the plurality of processing circuitries, each memory area associated with at least one of the plurality of processing circuitries;
• for at least one software thread of the one or more software threads, performing an analysis, comprising the plurality of thread statistical values thereof and using at least one statistical value of the plurality of thread statistical values collected for the at least one software thread, where a statistical value is a state value of the at least one software thread, to identify a preferred memory area of the plurality of memory areas;
• and
• configuring one of the at least one processing circuitry associated with the preferred memory area to execute the at least one software thread, wherein the one of the at least one processing circuitry associated with the preferred memory area is selected according to the at least one state value of the at least one software thread.

A software program product for executing a plurality of software threads, comprising:

• a non-transitory computer readable storage medium;
• and
• program instructions for in each of a plurality of iterations:
• while a plurality of processing circuitries executes the plurality of software threads, collecting for each software thread of one or more of the plurality of software threads a plurality of thread statistical values indicative of a plurality of memory accesses to at least some of a plurality of memory areas performed when executing the software thread, where the plurality of memory areas are connected to the plurality of processing circuitries, each memory area associated with at least one of the plurality of processing circuitries;
• for at least one software thread of the one or more software threads, performing an analysis, comprising the plurality of thread statistical values thereof and using at least one statistical value of the plurality of thread statistical values collected for the at least one software thread, where a statistical value is a state value of the at least one software thread, to identify a preferred memory area of the plurality of memory areas;
• and
• configuring one of the at least one processing circuitry associated with the preferred memory area to execute the at least one software thread, wherein the one of the at least one processing circuitry associated with the preferred memory area is selected according to the at least one state value of the at least one software thread;
• wherein the program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.