US 12,613,731 B2 · Pipeline arbitration

Abstract

A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

Claims20

Dependent claims

A circuit, comprising:

a cache subsystem that includes:
a first set of buffers including a first buffer associated with blocking transactions and a second buffer associated with non-blocking transactions;
a second set of buffers;
a multiplexer configured to transmit transactions from the first set of buffers to the second set of buffers;
and
an arbitration circuit coupled to the multiplexer and configured to:
determine that a first transaction of the blocking transactions is stored in the first buffer;
attempt to transmit the first transaction from the first buffer to the second set of buffers;
determine whether a second transaction of the non-blocking transactions is stored in the second buffer;
and
based on determining that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers;
and
cause the multiplexer to transmit the second transaction to the second set of buffers.

11 more elements

A system, comprising:

a set of transaction requestors configured to provide transactions including blocking transactions and non-blocking transactions;
and
a cache subsystem configured to receive the transactions and including:
a first set of buffers including a first buffer configured to store the blocking transactions and a second buffer configured to store the non-blocking transactions;
a second set of buffers;
a multiplexer configured to provide the transactions from the first set of buffers to the second set of buffers;
and
an arbitration circuit coupled to the multiplexer and configured to:
determine that a first transaction of the blocking transactions is stored in the first buffer;
attempt to transmit the first transaction from the first buffer to the second set of buffers;
determine whether a second transaction of the non-blocking transactions is stored in the second buffer;
and
based on determining that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers;
and
cause the multiplexer to transmit the second transaction to the second set of buffers.

13 more elements

Dependencies are inferred from the claim text.

Pipeline arbitration

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Pipeline arbitration

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Abstract

Claims20