Hardware accelerated machine learning
AssigneeIntel Corporation
InventorsJeremy Bruestle, Choong Ng
Life of this patent
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Abstract
A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.
Claims11
An apparatus comprising:
- a hardware accelerator, comprising:
- a plurality of circuitries to execute instructions associated with machine learning operations;
- a local memory comprising a plurality of dual-ported static random-access memory (SRAM), banks to store data associated with one or more of the instructions;
- circuitry to permute a first plurality of source data elements associated with a first multidimensional array in accordance with a permutation pattern included with a matrix multiplication instruction and route the first plurality of source data elements to the plurality of circuitries;
- the plurality of circuitries, coupled to the circuitry to obtain the first plurality of source data elements, to perform a plurality of parallel multiply-accumulate (MAC) operations in accordance with the matrix multiplication instruction, each of the plurality of parallel MAC operations comprising:
- multiplying a first source data element of the first plurality of source data elements provided by the circuitry to permute and a second source data element of a second plurality of source data elements associated with a second multidimensional array to generate a product, and
- adding the product to an accumulation value to generate a result value, the first source data element and the second source data element each having a first bit width and the accumulation value having a second bit width at least twice the first bit width.
Dependencies are inferred from the claim text.