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US 12,613,703 B2Granted
Tightly-coupled slice target file data for fused instructions
AssigneeInternational Business Machines Corporation
InventorsDung Q. Nguyen, Brian W. Thompto, Jose E. Moreira, Jessica Hui-Chun Tseng, Pratap C. Pattnaik, Kattamuri Ekanadham, Manoj Kumar
Life of this patent
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Abstract
A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with two register tags, write the two register tags into a mapper, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation unit (VSU), and execute the two instructions.
Claims15
A system comprising:
- a memory;
- and
- a processor in communication with the memory, the processor being configured to perform a process comprising:
- determining that two adjacent scalar instructions may be combined based on a processing power of the processor and a size of the instructions;
- fusing the two adjacent scalar instructions into a fused instruction pair;
- transmitting the fused instruction pair to instruction sequencing unit (ISU) circuitry on a pair lane;
- dispatching the fused instruction pair to a mapper, and an issue queue;
- mapping, with the mapper, the two adjacent scalar instructions with two register tags;
- writing the two register tags into the mapper with an even instruction tag (ITAG) and an odd ITAG;
- transmitting by an instruction dispatch unit (IDU) the even ITAG to the ISU circuitry;
- writing, by the ISU circuitry, the fused instruction pair into the issue queue;
- broadcasting the even ITAG to the mapper and the issue queue, wherein the even ITAG has a fused indicator;
- comparing, by the issue queue and the mapper, the even ITAG for an even instruction, and flipping a least significant bit of the even ITAG to generate the odd ITAG to compare against an odd instruction;
- issuing the fused instruction pair to a vector-scalar transformation unit (VSU), including issuing the fused instruction pair to the VSU when all six operands are ready;
- executing the fused instruction pair;
- and
- writing, by completion logic circuitry, scalar results for the fused instruction pair into both a right half side of a slice target file (STF) and a left half side of the STF, wherein the results are bypassed to a fused scalar pair at operand forwarding multiplexers.
14 more elements
A method comprising:
- determining that two adjacent scalar instructions may be combined based on a processing power of the processor and a size of the instructions;
- fusing the two adjacent scalar instructions into a fused instruction pair;
- transmitting the fused instruction pair to instruction sequencing unit (ISU) circuitry on a pair lane;
- dispatching the fused instruction pair to a mapper, and an issue queue;
- mapping, with the mapper, the two adjacent scalar instructions with two register tags;
- writing the two register tags into the mapper with an even instruction tag (ITAG) and an odd ITAG;
- transmitting by an instruction dispatch unit (IDU) the even ITAG to the ISU circuitry;
- writing, by the ISU circuitry, the fused instruction pair into the issue queue;
- broadcasting the even ITAG to the mapper and the issue queue, wherein the even ITAG has a fused indicator;
- comparing, by the issue queue and the mapper, the even ITAG for an even instruction, and flipping a least significant bit of the even ITAG to generate the odd ITAG to compare against an odd instruction;
- issuing the fused instruction pair to a vector-scalar transformation unit (VSU), including issuing the fused instruction pair to the VSU after determining that all six operands are ready;
- executing the fused instruction pair;
- and
- writing, by completion logic circuitry, scalar results for the fused instruction pair into both a right half side of a slice target file (STF) and a left half side of the STF, wherein the results are bypassed to a fused scalar pair at operand forwarding multiplexers.
11 more elements
A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method, the method comprising:
- determining that two adjacent scalar instructions may be combined based on a processing power of the processor and a size of the instructions;
- fusing the two adjacent scalar instructions into a fused instruction pair;
- transmitting the fused instruction pair to instruction sequencing unit (ISU) circuitry on a pair lane;
- dispatching the fused instruction pair to a mapper, and an issue queue;
- mapping, with the mapper, the two adjacent scalar instructions with two register tags;
- writing the two register tags into the mapper with an even instruction tag (ITAG) and an odd ITAG;
- transmitting by an instruction dispatch unit (IDU) the even ITAG to the ISU circuitry;
- writing, by the ISU circuitry, the fused instruction pair into the issue queue;
- broadcasting the even ITAG to the mapper and the issue queue, wherein the even ITAG has a fused indicator;
- comparing, by the issue queue and the mapper, the even ITAG for an even instruction, and flipping a least significant bit of the even ITAG to generate the odd ITAG to compare against an odd instruction;
- issuing the fused instruction pair to a vector-scalar transformation unit (VSU), including issuing the fused instruction pair to the VSU when all six operands are ready;
- executing the fused instruction pair;
- and
- writing, by completion logic circuitry, scalar results for the fused instruction pair into both a right half side of a slice target file (STF) and a left half side of the STF, wherein the results are bypassed to a fused scalar pair at operand forwarding multiplexers.
11 more elements
Dependencies are inferred from the claim text.