Apparatus and method for vector packed concatenate and shift of specific portions of quadwords

An apparatus comprising:

• a first source register to store a first plurality of data elements;
• a second source register to store a second plurality of data elements;
• a third source register to store one or more shift values;
• decoder circuitry to decode a first instruction specifying the first, second, and third source registers, a direction of bit-shifting, and a number of bits to be concatenated, wherein the first and second plurality of data elements in the first and second source registers each comprises a plurality of fields;
• and
• execution circuitry to execute the decoded first instruction, the execution circuitry comprising:
• concatenation circuitry to concatenate a first field from the plurality of fields within each of the first plurality of data elements with a second field from the plurality of fields within a corresponding data element of the second plurality of data elements based on the number of bits specified in the first instruction to generate a plurality of concatenated results;
• and
• shift circuitry to shift each of the plurality of concatenated results in the direction of bit-shifting specified in the first instruction by a number of bit positions specified by a corresponding one of the one or more shift values to generate a plurality of shifted results,
• wherein a select plurality of bits from each of the plurality of shifted results is stored in a corresponding data element position of a destination register.