Back to results
US 12,613,700 B2Granted
Zero extended 52-bit integer fused multiply add and subtract instructions
AssigneeIntel Corporation
InventorsFabian Boemer, Vinodh Gopal, Gelila Seifu, Sejun Kim, Jack Crawford
Life of this patent
Estimating the term…
Abstract
A processor includes an instruction set architecture that having instructions to perform data parallel multiply on a set of 52-bit integers and further instructions that additionally perform an add or subtract on intermediate products of the data parallel multiply. A 52-bit result of the operations is then zero extended to 64-bits.
Claims9
A processor comprising:
- first circuitry to decode an instruction, the instruction to indicate a first source operand, a second source operand, a third source operand and a destination operand;
- and
- second circuitry to perform operations corresponding to the instruction, including to:
- perform an element-wise multiply on 52-bit data values in corresponding 64-bit data elements of the second source operand and the third source operand to generate a set of 104-bit intermediate products;
- and
- when the instruction has a first opcode:
- zero-extend high 52 bits of the set of 104-bit intermediate products to first 64-bit values;
- perform an arithmetic operation on the first 64-bit values and second 64-bit values within 64-bit data elements of the first source operand to generate 64-bit intermediate values;
- zero-extend low 52 bits of the 64-bit intermediate values to generate 64-bit result values;
- and
- store the 64-bit result values in the destination operand;
- wherein the second circuitry is further to:
- when the instruction has a different opcode:
- perform an arithmetic operation on the high 52 bits of the 104-bit intermediate products and low 52 bits of the 64-bit data elements of the first source operand to generate 52-bit or 53-bit intermediate values;
- zero-extend the 52-bit or 53-bit intermediate values to generate 64-bit data values;
- and
- store the 64-bit data values in the destination operand.
14 more elements
A method comprising:
- fetching and decoding an instruction, the instruction having multiple source operands and one or more destination operands;
- and
- performing operations corresponding to the instruction, including:
- performing an element-wise multiply on 52-bit data values in corresponding 64-bit data elements of two of the multiple source operands to generate a set of 104-bit intermediate products;
- zero-extending high 52 bits of the set of 104-bit intermediate products to generate 64-bit result values when the instruction has a first opcode;
- zero-extending low 52 bits of the set of 104-bit intermediate products to generate the 64-bit result values when the instruction has a different opcode than the first opcode;
- and
- packing the 64-bit result values into a packed data type and storing the packed data type in the one or more destination operands,
- wherein performing the operations corresponding to the instruction additionally includes, when the instruction has a third opcode:
- zero-extending the high 52 bits of the 104-bit intermediate products to generate first 64-bit intermediate values;
- adding to or subtracting from the first 64-bit intermediate values using 64-bit data elements of an additional source operand of the multiple source operands to generate second 64-bit intermediate values;
- and
- zero-extending the low 52 bits of the second 64-bit intermediate values to the 64-bit result values before packing the 64-bit result values into the packed data type.
10 more elements
A processor comprising:
- first circuitry to decode a first instruction and a second instruction, the first instruction to indicate a first source operand, a second source operand, a third source operand and a first destination operand, the second instruction to indicate a fourth source operand, a fifth source operand, a sixth source operand and a second destination operand;
- and
- second circuitry to perform operations corresponding to the first instruction, including to:
- perform an element-wise multiply on 52-bit data values in corresponding 64-bit data elements of the second source operand and the third source operand to generate a first set of 104-bit intermediate products;
- zero-extend high 52 bits of the first set of 104-bit intermediate products to first 64-bit values;
- perform an arithmetic operation on the first 64-bit values and second 64-bit values within 64-bit data elements of the first source operand to generate 64-bit intermediate values;
- zero-extend low 52 bits of the 64-bit intermediate values to generate 64-bit result values;
- and
- store the 64-bit result values in the first destination operand,
- wherein the second circuitry is further to perform operations corresponding to the second instruction, including to:
- perform an element-wise multiply on 52-bit data values in corresponding 64-bit data elements of the fifth source operand and the sixth source operand to generate a second set of 104-bit intermediate products;
- perform an arithmetic operation on high 52 bits of the second set of 104-bit intermediate products and low 52 bits of 64-bit data elements of the fourth source operand to generate 52-bit or 53-bit intermediate values;
- zero-extend the 52-bit or 53-bit intermediate values to generate second 64-bit result values;
- and
- store the second 64-bit result values in the second destination operand.
12 more elements
Dependencies are inferred from the claim text.