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US 12,613,699 B2Granted
DMA controller and LSU to transpose data arrays stored in main memory for storage in processor registers
AssigneeSony Interactive Entertainment Inc.
InventorJeppe Oland
Life of this patent
Estimating the term…
Abstract
One or more hardware elements operate on an array of data from a memory to generate a shuffled array of data. A subsequent of hardware operations on the shuffled array of data produces a transposed array of data in which rows and columns of the array of data are transposed. A load-store unit may then load the array of transposed data into a plurality of processor registers.
Claims17
A computer system comprising:
- a processor having a plurality of registers;
- a main memory;
- a local memory;
- a direct memory access (DMA) controller configured to perform one or more operations on an array of data from the memory to generate a shuffled array of data from the array of data from the memory and store the shuffled array in the local memory;
- and
- a load-store unit configured to perform one or more operations on the shuffled array of data stored in the local memory to produce a transposed array of data in which rows and columns of the array of data are transposed, and wherein the load-store unit is configured to load the transposed array of data into the plurality of registers.
3 more elements
A method for transferring transposed data from a memory to a plurality of registers, comprising:
- performing one or more operations on an array of data from a memory to generate a shuffled array of data with a direct memory access controller;
- and
- performing one or more operations on the shuffled array of data with a load-store unit to produce a transposed array of data in which rows and columns of the array of data are transposed;
- and
- loading the array of transposed data into a plurality of registers of a processor with the load-store unit.
2 more elements
A computer system comprising:
- a main memory;
- a direct memory access (DMA) controller;
- a load-store unit (LSU), and;
- a processor having a plurality of registers;
- wherein the DMA controller, LSU, and processor include hardware configured to perform one or more operations on an array of data from the memory to generate a shuffled array of data from the array of data from the memory and to perform one or more operations on the shuffled array of data to produce a transposed array of data in which rows and columns of the array of data are transposed, and wherein the load-store unit is configured to load the transposed array of data into the processor's plurality of registers.
2 more elements
Dependencies are inferred from the claim text.