Apparatus and method for hiding vector load latency in a time-based vector coprocessor

A processor including hardware that comprises:

• circuitry to receive and decode a first vector load instruction and dispatch the first vector load instruction to a first functional unit or to a load-store unit;
• a re-order buffer that receives decoded instructions in order and records completion of instructions and cancels or validates vector instructions when a branch instruction is mispredicted;
• and
• a vector coprocessor comprising:
• a vector time counter generating a vector time count representing a current time of the vector coprocessor, wherein the vector time count is incremented periodically;
• a vector load-store buffer coupled to the vector time counter and the load-store unit to select a first entry for storage of first vector load data and to store a schedule time corresponding to the vector time count to write the first vector load data to a vector register file;
• vector decode circuitry that receives the first vector load instruction upon validation by the re-order buffer and issues the first vector load instruction;
• a vector register scoreboard coupled to the vector time counter and the vector decode circuitry to receive the first vector load instruction and to provide a corresponding write time or read time for each operand of the first vector load instruction, wherein the write time corresponds to a future vector time count in which no data dependency is violated;
• a vector time-resource matrix coupled to the vector time counter and the vector register scoreboard to receive the write time, and further coupled to the vector load-store buffer to read a first entry, and select a worst case time for updating the schedule time in the vector load-store unit, and further coupled to vector issue circuitry to check the vector time-resource matrix for availability of a write port at the schedule time and to issue the first vector load instruction if the write port is available, or to stall the first vector load instruction in the vector issue circuitry to increment the write time and to access the write port of the vector time-resource matrix again in a next cycle and to update the schedule time in the vector load-store buffer;
• and
• wherein the vector issue circuitry is further coupled to the vector register file to write vector data associated with the first vector load instruction if the vector data is valid when the vector time count is the same as the schedule time and if the vector data is not valid to stop counting by the vector time counter until the vector data is valid.

A computer program product stored on a non-transitory computer readable storage medium and including computer system instructions for causing a computer system to execute a method that is executable by a vector coprocessor for processing a committed coprocessor vector load instruction received from a processor that operates in accordance with a time count that is incremented with each clock cycle of a clock unit, the method comprising:

• generating a vector time count by incrementing a vector time counter with each clock cycle of the clock unit;
• receiving a vector load instruction from the processor and allocating an entry in a vector load-store buffer wherein the vector load-store buffer is coupled to the vector time counter and comprises a plurality of entries, each of the entries corresponding to a load instruction or a store instruction;
• processing of the committed coprocessor vector load instruction in the vector coprocessor to determine a schedule time in reference to the vector time count of the vector load instruction to write a vector register file when vector load data is valid in the entry of the vector load-store buffer;
• freezing the vector time count if the vector load data is not returned at the schedule time;
• and
• unfreezing the vector time counter when the vector load data is received and transferred to the vector register file.