Memory devices, computing devices, and methods for in-memory computing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Fu Lee, Po-Hao Lee, Yi-Chun Shih, Yu-Der Chih
Life of this patent
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Abstract
A memory device includes a computing-in-memory macro and a clock generating circuit. The computing-in-memory macro is configured to perform in-memory computing based on a first clock signal. The clock generating circuit is arranged within the computing-in-memory macro and configured to generate the first clock signal. A frequency of the first clock signal is modified according to a condition of the computing-in-memory macro to cause the first clock signal to conform to an operation speed of the in-memory computing.
Claims20
A memory device, comprising:
- a computing-in-memory macro configured to perform in-memory computing based on a first clock signal;
- and
- a clock generating circuit arranged within the computing-in-memory macro and configured to generate the first clock signal, wherein a frequency of the first clock signal is modified according to a condition of the computing-in-memory macro to cause the first clock signal to conform to an operation speed of the in-memory computing;
- and
- an input buffer circuit configured to receive input data based on a second clock signal, and to output the input data in the computing-in-memory macro based on the first clock signal.
A computing device, comprising:
- a memory array comprising a plurality of memory cells for storing data for a multiply accumulate operation;
- a clock generating circuit configured to generate a first clock signal for performing the multiply accumulate operation, wherein a frequency of the first clock signal is determined based on a process-voltage-temperature (PVT) condition to conform to an operation speed of the multiply accumulate operation;
- an input buffer circuit configured to receive input data from an input channel, and to output the input data to the memory array;
- and
- an output buffer circuit configured to receive output data resulting from the multiply accumulate operation from the memory array based on the first clock signal, and to output the output data to an output channel based on a second clock signal.
A method for in-memory computing, comprising:
- tracking a process-voltage-temperature condition of a computing-in-memory macro for performing a multiply accumulate operation;
- generating a first clock signal and adjusting a frequency of the first clock signal to conform to an operation speed of the multiply accumulate operation based on the process-voltage-temperature condition;
- receiving input data, by an input buffer circuit, based on a second clock signal from an input channel, wherein the first clock signal and the second clock signal are asynchronous clock signals;
- and
- transmitting the input data, by the input buffer circuit, to the computing-in-memory macro and receiving, by an output buffer circuit, output data from the computing-in-memory macro based on the first clock signal.
Dependencies are inferred from the claim text.