Back to results
US 12,613,675 B2Granted
AI calculation circuit
AssigneeShenzhen Suanhai Technology Co. Ltd.
InventorsChia-Lin Lu, Yuan-Hsiang Kuo, Wei-Chun Chang, Tsung-Hsien Lin, Chin-Chung Yen
Life of this patent
Estimating the term…
Abstract
An artificial intelligence (AI) calculation circuit is provided. The AI calculation circuit can support various integer and floating-point calculations through the adjustment of circuit configuration. Integer multiplication and floating-point mantissa multiplication share the multiplication unit, integer comparison and floating-point comparison share the same comparison unit, integer addition and floating-point addition share the same addition unit.
Claims7
An AI calculation circuit, characterized in comprising:
- a plurality of calculation circuits, each comprising:
- a floating-point multiplication module, comprising a first selection unit, a second selection unit and a multiplication unit, wherein a first input end of the first selection unit is configured to receive a first numeric data, a second input end of the first selection unit is configured to receive a plurality of mantissa bits of the first numeric data, a first input end of the second selection unit is configured to receive a second numeric data, a second input end of the second selection unit is configured to receive a plurality of mantissa bits of the second numeric data, and the multiplication unit is coupled to the first selection unit and the second selection unit;
- a floating-point addition module, comprising a comparison unit, a third selection unit, a fourth selection unit and an addition unit, wherein the comparison unit is configured to receive the first numeric data and the second numeric data, a first input end of the third selection unit is configured to receive the first numeric data, a second input end of the third selection unit is configured to receive the mantissa bits of the first numeric data, a first input end of the fourth selection unit is configured to receive the second numeric data, a second input end of the fourth selection unit is configured to receive the mantissa bits of the second numeric data, and the addition unit is coupled to the third selection unit and the fourth selection unit;
- and
- a storage module coupled to the floating-point multiplication module and the floating-point addition module,
- wherein when the format of the first numeric data is integer format, the first selection unit, the second selection unit, the third selection unit and the fourth selection unit selectively output through the first input ends;
- when the format of the first numeric data is floating-point format, the first selection unit, the second selection unit, the third selection unit and the fourth selection unit selectively output through the second input ends.
4 more elements
Dependencies are inferred from the claim text.