Low pass through voltage on lower tier wordlines for read disturb improvement
AssigneeMicron Technology, Inc.
InventorsGo Shikata, Xiangyu Yang, Ching-Huang Lu
Life of this patent
Estimating the term…
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AssigneeMicron Technology, Inc.
InventorsGo Shikata, Xiangyu Yang, Ching-Huang Lu
Estimating the term…
A memory device can include a memory array coupled with control logic. The control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. The control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. The control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. The control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.
A memory device comprising:
A memory device comprising:
A method comprising:
Dependencies are inferred from the claim text.