Memory controller fractonal bandwidth adjustment for critical and non- critical components

A data processing system, comprising:

• a memory;
• a plurality of processing components configured to access the memory by one or more memory access operations;
• and
• a memory controller for controlling access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system, wherein the memory controller comprises:
• a controller configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations;
• a monitor device configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system;
• wherein the controller is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitor device;
• wherein based on a memory access operation for a critical processing component having exceeded a corresponding timing requirement, the controller is further configured to:
• register one or more current bandwidth values of corresponding one or more non-critical processing components associated with most recent transactions, as corresponding one or more maximum bandwidth values;
• reduce, by a configurable amount, the one or more current bandwidth values of the corresponding one or more non-critical processing components associated with the most recent transactions;
• and
• wherein each identity of the one or more non-critical processing components associated with the most recent transactions is recorded in a list stored in a first-in-first-out (FIFO) buffer, and the controller is configured to retrieve the list from the FIFO buffer and determine the configurable amount based on the list and a respective current bandwidth setting.

A method for controlling access of a memory with a memory access bandwidth by a plurality of processing components of a data processing system, wherein the method which is applied to a memory controller comprises:

• allocating a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations;
• obtaining timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system;
• and
• adjusting for one or more of the plurality of processing components the respective fraction of the memory access bandwidth based on the obtained timing information;
• wherein based on a memory access operation for a critical processing component having exceeded a corresponding timing requirement, the method further comprises:
• registering one or more current bandwidth values of corresponding one or more non-critical processing components associated with most recent transactions, as corresponding one or more maximum bandwidth values;
• reducing, by a configurable amount, the one or more current bandwidth values of the corresponding one or more non-critical processing components associated with the most recent transactions;
• and
• wherein each identity of the one or more non-critical processing components associated with the most recent transactions is recorded in a list stored in a first-in-first-out (FIFO) buffer, and the controller is configured to retrieve the list from the FIFO buffer and determine the configurable amount based on the list and a respective current bandwidth setting.