Memory controller and memory data receiving method

A memory controller, arranged to access a memory device, the memory controller comprising:

• a receiving circuit, arranged to receive a data signal and a data strobe signal from the memory device, the receiving circuit comprising:
• a sampling circuit, arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal, in order to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal;
• and
• a comparison circuit, arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result;
• wherein the plurality of delayed versions of the data strobe signal comprise a first delayed data strobe signal generated according to a first delay value, a second delayed data strobe signal generated according to a second delay value, and a third delayed data strobe signal generated according to a third delay value;
• the sampling circuit samples the data signal or the delayed data signal according to the first delayed data strobe signal, the second delayed data strobe signal, and the third delayed data strobe signal in sequence, to generate a first sampling value, a second sampling value, and a third sampling value, respectively;
• and the first delay value is smaller than the second delay value, and the second delay value is smaller than the third delay value.