Techniques for operating hybrid blocks in a memory device

A memory device, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory block being configured to program and erase data according to both a one bit per memory cell (SLC) storage scheme and a multiple bits per memory cell storage scheme;
• control circuitry configured to;
• receive a command to write data to the memory cells of the memory block in the multiple bits per memory cell storage scheme,
• perform a sensing operation on a selected word line in the memory block using at least one reference voltage to determine if data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme,
• in response to a determination that the data contained in the memory block is in the SLC storage scheme, pre-program the memory cells of the memory block and then erase the memory cells, and
• in response to a determination that the data contained in the memory block is in the multiple bits per memory cell storage scheme, erase the memory cells without pre-programming the memory cells.

An apparatus, comprising:

• a hybrid block that includes an array of memory cells that are arranged in a plurality of word lines, the hybrid block being configured to program and erase data according to both a one bit per memory cell (SLC) storage scheme and a three bits per memory cell (TLC) storage scheme;
• a programming and erasing means configured to;
• receive a command to write data to the memory cells of the hybrid block in the multiple bits per memory cell storage scheme,
• perform a sensing operation on a selected word line in the hybrid block using at least one reference voltage to determine if data stored in the hybrid block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme,
• in response to a determination that the data contained in the hybrid block is in the SLC storage scheme, pre-program the memory cells of the memory block and then erase the memory cells, and
• in response to a determination that the data contained in the hybrid block is in the multiple bits per memory cell storage scheme, erase the memory cells without pre-programming the memory cells.