Back to results
US 12,613,633 B2Granted
Data input and output method and semiconductor device using the same
AssigneeSK hynix Inc.
InventorsDong Yoon Ka, Min Cheol Park
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory circuit including a plurality of mats and a meta region and configured to block output of first internal data stored in the plurality of mats based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address during normal mode and configured to output second internal data from the meta region and a data input and output circuit configured to generate a plurality of data from the first internal data and the second internal data based on a plurality of shifting signals.
Claims29
A semiconductor device comprising:
- a memory circuit comprising a first mat, a second mat, a third mat, a fourth mat, and a meta region and configured to block output of one of first internal data, second internal data, third internal data, and fourth internal data stored in the first mat, the second mat, the third mat, and the fourth mat based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address during normal mode and configured to output fifth internal data from the meta region;
- and
- a data input and output circuit configured to generate first data, second data, third data, and fourth data from the first internal data, the second internal data, the third internal data, the fourth internal data, and the fifth internal data based on a plurality of shifting signals.
A semiconductor device comprising:
- a memory circuit comprising a first mat, a second mat, a third mat, a fourth mat, and a meta region, configured to repair a column line at a location where a fail occurred when an address has a logic level combination that selects a column line at a location where a fail occurred in normal mode, configured to block output of one of first internal data, second internal data, third internal data, and fourth internal data stored in the first mat, the second mat, the third mat, and the fourth mat based on a column signal and a plurality of flag signals that are generated by performing a computational operation on the address, and configured to output fifth internal data from the meta region;
- and
- a data input and output circuit configured to generate first data, second data, third data, and fourth data from the first internal data, the second internal data, the third internal data, the fourth internal data, and the fifth internal data based on a plurality of shifting signals.
A semiconductor device comprising:
- a memory control circuit configured to generate a column signal by performing a computational operation on an address based on a meta control signal and configured to generate a plurality of masking signals by performing the computational operation on the address;
- a memory circuit comprising a first mat, a second mat, a third mat, a fourth mat, and a meta region, configured to output first internal data, second internal data, third internal data, and fourth internal data stored in the first mat, the second mat, the third mat, and the fourth mat based on the column signal in normal mode, and configured to output fifth internal data from the meta region;
- and
- a data input and output circuit configured to generate first data, second data, third data, and fourth data based on the first internal data, the second internal data, the third internal data, the fourth internal data, and the fifth internal data, and configured to generate the first data, the second data, the third data, and the fourth data by blocking output of one of the first internal data, the second internal data, the third internal data, the fourth internal data based on the plurality of masking signals.
1 more element
A data input and output method comprising:
- outputting first internal data, second internal data, third internal data, and fourth internal data stored in a first mat, a second mat, a third mat, and a fourth mat based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address in normal mode, blocking one of the first internal data, the second internal data, the third internal data, and the fourth internal data, and outputting fifth internal data stored in a meta region;
- and
- generating first data, second data, third data, and fourth data from the first internal data, the second internal data, the third internal data, the fourth internal data, and the fifth internal data based on a plurality of shifting signals and outputting the first data, the second data, the third data, and the fourth data.
A semiconductor device comprising:
- a memory circuit comprising a plurality of mats and a meta region and configured to block output of first internal data stored in the plurality of mats based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address during normal mode and configured to output second internal data from the meta region;
- and
- a data input and output circuit configured to generate a plurality of data from the first internal data and the second internal data based on a plurality of shifting signals.
Dependencies are inferred from the claim text.