Stack memory devices configured to communicate via packets
AssigneeSK hynix Inc.
InventorChoung Ki Song
Life of this patent
Estimating the term…
Abstract
A stack memory device includes a physical layer configured to receive write data, a write valid signal, and a transmission write clock signal from an external device and transmit read data, a read valid signal, and a transmission read clock signal to the external device, a selector configured to output a signal output from the physical layer through a first channel or a second channel, based on a channel selection signal, and a control layer configured to receive an output signal of the selector through the first channel or the second channel to generate a control command and an address for controlling a write operation or a read operation within a core chip.
Claims19
A stack memory device comprising:
- a physical layer configured to receive write data, a write valid signal, and a transmission write clock signal from an external device and transmit read data, a read valid signal, and a transmission read clock signal to the external device;
- a selector configured to output a signal output from the physical layer through a first channel or a second channel, based on a channel selection signal;
- and
- a control layer configured to receive an output signal of the selector through the first channel or the second channel to generate a control command and an address for controlling a write operation or a read operation within a core chip,
- wherein the control layer comprises a first memory control group configured to receive the signal output from the physical layer through the first channel to generate the control command and the address when the channel selection signal is at a first logic level.
A stack memory device comprising:
- a first physical layer configured to receive a signal from an external device and transmit a signal to the external device;
- a first selector configured to output a signal output from the first physical layer through a first channel or a second channel, based on a channel selection signal;
- a first memory control group configured to receive the signal output from the first physical layer through the first channel through the first selector to generate a control command and an address, based on the channel selection signal;
- and
- a second memory control group configured to receive the signal output from the first physical layer through the second channel through the first selector to generate the control command and the address, based on the channel selection signal,
- wherein the first selector is configured to output the signal output from the first physical layer to the first memory control group through the first channel when the channel selection signal is at a first logic level.
A stack memory device comprising:
- a base chip;
- and
- a core chip stacked on the base chip and electrically connected to the base chip,
- wherein the base chip comprises:
- a physical layer configured to receive a signal from an external device and transmit a signal to the external device;
- a selector configured to output a signal output from the physical layer through a first channel or a second channel, based on a channel selection signal;
- and
- a control layer configured to receive an output signal of the selector through the first channel or the second channel to generate a control command and an address for controlling a write operation or a read operation within the core chip,
- wherein the control layer comprises a first memory control group configured to receive the signal output from the physical layer through the first channel to generate the control command and the address when the channel selection signal is at a first logic level.
Dependencies are inferred from the claim text.