US 12,613,568 B2Granted

Power state management for system-on-chip

AssigneeQUALCOMM Incorporated

InventorsShriharsha Chebbi, Lakshmi Narayana Panuku, Prashanth Kumar Kakkireni, Arun Gothekar, Anirudh Ghayal, Sriram Hariharan

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Abstract

This disclosure provides systems, methods, and devices for power state transitions with multiple chiplets. In a first aspect, a method of image processing includes receiving an indication to enter a partial sleep state for a processor comprising a first main domain and a first separate domain coupled through a different power supply path than the first main domain; and in response to the indication, transitioning, by the processor, the first main domain to a sleep state while the first separate domain remains in an active state for receiving processing requests or monitoring the first main domain. Other aspects and features are also claimed and described.

Claims17

Dependent claims

A method, comprising:

receiving an indication to enter a sleep state for at least one processor comprising a first main domain and a first separate domain coupled through a different power supply path than the first main domain;
in response to the indication, transitioning, by the at least one processor, the first main domain from an active state configured to perform an automotive function to a first sleep state while the first separate domain remains in the active state to monitor entry of the first sleep state of the first main domain, wherein the transitioning of the first main domain to the first sleep state comprise:
in response to the first main domain being in an island state or an off state, transitioning, by the at least one processor, the first main domain to the active state;
and
transitioning the first main domain from the active state to the first sleep state;
and
after the entry of the first sleep state of the first main domain, transitioning the first separate domain to a second sleep state, the second sleep state associated with a higher voltage than the first sleep state.

4 more elements

An apparatus, comprising:

a memory storing processor-readable code;
and
at least one processor coupled to the memory, the at least one processor comprising a first main domain and a first separate domain coupled through a different power supply path than the first main domain, the at least one processor configured to execute the processor-readable code to cause the at least one processor to perform operations including:
receiving an indication to enter a sleep state for the at least one processor;
in response to the indication, transitioning the first main domain from an active state configured to perform an automotive function to a first sleep state while the first separate domain remains in the active state to monitor entry of the first sleep state of the first main domain, wherein the transitioning of the first main domain to the first sleep state comprise:
in response to the first main domain being in an island state or an off state, transitioning the first main domain to the active state;
and
transitioning the first main domain from the active state to the first sleep state;
and
after the entry of the first sleep state of the first main domain, transitioning the first separate domain to a second sleep state, the second sleep state associated with a higher voltage than the first sleep state.

7 more elements

A system, comprising:

a primary chiplet including a first main domain and a first separate domain, the first separate domain coupled through a different power supply path than the first main domain,
wherein the first main domain is configured to:
receive an indication to enter a sleep state for the primary chiplet;
in response to the indication, transition from an active state configured to perform an automotive function to a first sleep state while the first separate domain remains in the active state to monitor entry of the first sleep state of the first main domain,
in response to the first main domain being in an island state or an off state, transition to the active state;
and
transition from the active state to the first sleep state;
and
wherein the first separate domain is configured to:
after the entry of the first sleep state of the first main domain, communicate with a microcontroller unit (MCU);
and
transition to a second sleep state, the second sleep state associated with a higher voltage than the first sleep state.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/670,526Filed 21 May 2024
Published: US 2025/0362733 A127 Nov 2025
Granted: 28 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/3296
Power saving characterised by the action undertaken: by lowering the supply or operating voltage
G06F 1/3206
Power management, i.e. event-based initiation of a power-saving mode: monitoring of events, devices or parameters that trigger a change in power…
G06F 1/3293
Power saving characterised by the action undertaken: by switching to a less power-consuming processor, e.g. sub-CPU