Method of manufacturing nitride semiconductor device

A manufacturing method of a nitride semiconductor device, the manufacturing method comprising:

• introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region;
• forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region, the second nitride semiconductor layer being coherently grown and formed, and the p type impurity introduction region being formed at a position exposed on the upper surface of the first nitride semiconductor layer;
• performing an anneal treatment after the second nitride semiconductor layer is formed on the first nitride semiconductor layer and on the p type impurity introduction region at the position exposed on the upper surface of the first nitride semiconductor layer in a state where at least a part of the p type impurity introduction region is disposed in a two-dimensional electron gas layer of the first nitride semiconductor layer;
• and
• removing the second nitride semiconductor layer from the first nitride semiconductor layer after performing the anneal treatment, wherein:
• in the forming the second nitride semiconductor layer, the second nitride semiconductor layer is formed by stacking nitride semiconductor layers having different composition ratios,
• the first nitride semiconductor layer is made of GaN,
• the second nitride semiconductor layer is comprised of a lower second nitride semiconductor layer formed of InAlN that is adjacent to the first nitride semiconductor layer and an upper second nitride semiconductor layer formed of AlGaN and stacked on top of the lower second nitride semiconductor layer,
• an upper layer portion of the first nitride semiconductor layer becomes an n type region;
• at least a part of the p type impurity introduction region is disposed in the n type region of the first nitride semiconductor layer;
• and
• the anneal treatment is performed in a state where
• the upper layer portion of the first nitride semiconductor layer is the n type region, and
• the maximum concentration of the p type impurity introduced into the p type impurity introduction region is adjusted to be smaller than the maximum charge density in the two-dimensional electron gas layer.