Vertical MOSFET super junction device and method of manufacturing the same

A method of manufacturing a semiconductor device including a plurality of unit cells, the method comprising:

• (a) preparing a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type;
• (b) forming a pair of trenches in the drift region;
• (c) forming a pair of column regions of a second conductivity type opposite to the first conductivity type in the drift region so as to be separately adjacent to each other in a first direction in plan view;
• (d) forming a pair of gate electrodes in the pair of trenches via a gate insulating film, respectively;
• (e) forming a body region of the second conductivity type on a surface of the drift region;
• (f) forming a source region of the first conductivity type on a surface of the body region;
• (g) forming an interlayer insulating film on the semiconductor substrate so as to cover the pair of gate electrodes;
• (h) forming a pair of first holes and a second hole penetrating the interlayer insulating film and the source region such that bottoms thereof are located in the body region;
• and
• (i) forming a source wiring on the interlayer insulating film so as to fill the pair of first holes and the second hole,
• wherein the pair of trenches are formed between the pair of column regions in the first direction,
• wherein bottoms of the pair of trenches reach a position deeper than the body region,
• wherein each of the plurality of unit cells includes the semiconductor substrate, the drift region, the pair of trenches, the pair of column regions, the gate insulating film, the pair of gate electrodes, the body region, and the source region,
• wherein the two unit cells adjacent in the first direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region,
• wherein, in the first direction, a first distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is larger than a second distance between the pair of trenches in the one unit cell,
• wherein the pair of first holes are provided at positions overlapping the pair of column regions in plan view,
• wherein the second hole is formed between the pair of gate electrodes in the first direction,
• wherein each of the plurality of unit cells further includes the interlayer insulating film, the pair of first holes, the second hole, and the source wiring,
• wherein in the first direction, a third distance between one trench, which is located near the one column region, of the pair of trenches and one first hole, which overlaps the one column region in plan view, of the pair of first holes is larger than a fourth distance between the one trench and the second hole,
• wherein the pair of column regions, the pair of trenches, and the pair of first holes each extend in a second direction intersecting with the first direction in plan view, and
• wherein in (h), a plurality of the second holes is formed in the interlayer insulating film so as to be separately adjacent to each other in the second direction.