3D semiconductor devices and structures with functional units and pillars

A 3D device, said device comprising:

• a first level comprising first transistors, said first level comprising a first interconnect;
• a second level comprising second transistors, said second level overlaying said first level;
• at least four functional units;
• at least one SRAM (Static Random Access Memory) array,
• wherein each of said at least four functional units comprises a first circuit, said first circuit comprising a portion of said first transistors,
• wherein each of said at least four functional units comprises a second circuit, said second circuit comprising a portion of said second transistors,
• wherein each of said at least four functional units comprises a vertical connectivity structure, said vertical connectivity structure comprising a plurality of pillars,
• wherein said plurality of pillars provides electrical control connections between said first circuit and said second circuit,
• wherein each of said at least four functional units comprises at least one memory control circuit and at least one memory array,
• wherein said second level is bonded to said first level, and
• wherein said bonded comprises metal to metal bonding regions;
• and
• a third transistor and a fourth transistor,
• wherein said third transistor is electrically connected to said fourth transistor, and
• wherein said third transistor and said fourth transistor are at least 100 mm apart.

A 3D device, said device comprising:

• a first level comprising first transistors, said first level comprising a first interconnect;
• a second level comprising second transistors, said second level overlaying said first level;
• at least four functional units;
• at least one temperature sensor,
• wherein each of said at least four functional units comprises a first circuit, said first circuit comprising a portion of said first transistors,
• wherein each of said at least four functional units comprises a second circuit, said second circuit comprising a portion of said second transistors,
• wherein each of said at least four functional units comprises a vertical connectivity structure, said vertical connectivity structure comprising a plurality of pillars,
• wherein said plurality of pillars provides electrical control connections between said first circuit and said second circuit,
• wherein each of said at least four functional units comprises at least one memory control circuit and at least one memory array,
• wherein said second level is bonded to said first level, and
• wherein said bonded comprises metal to metal bonding regions;
• and
• a third transistor and a fourth transistor,
• wherein said third transistor is electrically connected to said fourth transistor, and
• wherein said third transistor and said fourth transistor are at least 100 mm apart.