Semiconductor device and method for manufacturing same
AssigneeChangxin Memory Technologies, Inc.
InventorsWei Chang, Qingsong Du
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Abstract
A semiconductor device includes: a semiconductor substrate and a memory cell located on a surface of the semiconductor substrate; the semiconductor substrate comprises a well area, an isolation structure, a first doped area and a second doped area; the isolation structure, the first doped area and the second doped area are located in the well area, and the isolation structure at least is located between the first doped area and the second doped area; the memory cell is located on a top surface of the second doped area and is electrically connected with the second doped area.
Claims14
A semiconductor device, at least comprising:
- a semiconductor substrate and a memory cell located on a surface of the semiconductor substrate, wherein,
- the semiconductor substrate comprises a well area, an isolation structure, a first doped area and a second doped area;
- the isolation structure, the first doped area and the second doped area are located in same well area, and the isolation structure at least is located between the first doped area and the second doped area;
- and
- the memory cell is located on a top surface of the second doped area and is electrically connected with the second doped area;
- the semiconductor device further comprises a first via and a bit line metal layer, wherein the bit line metal layer extends along a second direction and the bit line metal layer is sequentially arranged in a first direction, the bit line metal layer is connected with the memory cell through the first via and is configured for providing a read voltage or a write voltage to the memory cell;
- wherein the first doped area and the second doped area are sequentially arranged in the well area in the first direction, and the second doped area comprises a plurality of second doped sub-areas arranged in the first direction;
- the memory cell is formed on a top surface of each of the second doped sub-areas and electrically connected with each of the second doped sub-areas, wherein the bit line metal layer is connected with a second doped sub-area through the memory cell and the first metal layer.
A method for manufacturing a semiconductor device, comprising:
- providing a semiconductor substrate;
- forming a well area in the semiconductor substrate;
- forming, in same well area, a first doped area, a second doped area and an isolation structure at least being located between the first doped area and the second doped area;
- forming a memory cell on a top surface of the second doped area;
- the method for manufacturing the semiconductor device further comprises, forming a first via and a bit line metal layer on the second electrode layer of the memory cell, and the bit line metal layer being connected to the second doped area through the memory cell, wherein the bit line metal layer extends along a second direction and the bit line metal layer is sequentially arranged in a first direction, the bit line metal layer is connected with the memory cell through the first via and is configured for providing a read voltage or a write voltage to the memory cell;
- wherein the first doped area and the second doped area are sequentially arranged in the well area in the first direction, and the second doped area comprises a plurality of second doped sub-areas arranged in the first direction;
- the memory cell is formed on a top surface of each of the second doped sub-areas and electrically connected with each of the second doped sub-areas, wherein the bit line metal layer is connected with a second doped sub-area through the memory cell and the first metal layer.
Dependencies are inferred from the claim text.