Multi-storage element single-transistor crosspoint memory systems at low temperatures
AssigneeIntel Corporation
InventorsAbhishek Anil Sharma, Wilfred Gomes, Anand Murthy, Sagar Suthram, Tahir Ghani
Life of this patent
Estimating the term…
Abstract
Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor. A single common select transistor accesses information stored in an array of storage elements. Other arrays of storage elements on parallel storage lines can be coupled into a crosspoint array by source lines orthogonal to the storage lines. The storage elements may be non-volatile. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.
Claims19
A memory device, comprising:
- an access transistor comprising a channel between a source and a drain, wherein the access transistor is a non-planar transistor, and the channel is within one of a substantially vertical fin, a nanosheet, or a nanowire;
- a storage line coupled to the source or the drain, the storage line extending in a first direction;
- a plurality of storage elements, wherein individual ones of the storage elements comprise a first electrode, a second electrode, and a storage layer therebetween, and wherein each of the first electrodes of the individual ones of the first electrodes are coupled to the storage line;
- and
- a plurality of source lines, the source lines extending in a second direction substantially orthogonal to the first direction, wherein individual ones of the source lines are coupled to corresponding ones of the second electrodes.
An integrated circuit (IC) system, comprising:
- a power supply, the power supply coupled to an IC die, the IC die comprising:
- a plurality of storage lines extending in a first direction;
- a plurality of select transistors, wherein individual ones of the select transistors comprise a channel between a source and a drain, and individual ones of the sources or drains are coupled to individual ones of the storage lines;
- a plurality of source lines, the source lines extending in a second direction substantially orthogonal to the first direction;
- and
- an array of storage elements, wherein individual ones of the storage elements comprise a first electrode, a second electrode, and a storage layer therebetween, individual ones of the first electrodes are coupled to corresponding ones of the storage lines, and individual ones of the second electrodes are coupled to corresponding ones of the source lines.
A method, comprising:
- receiving a substrate, the substrate comprising a transistor;
- forming a storage line, the storage line coupled to a source or a drain of the transistor, and the storage line extending in a first direction;
- forming a plurality of storage elements over the storage line, wherein individual ones of the storage elements are coupled to the storage line, and individual ones of the storage elements comprise a first electrode, a second electrode, and a storage material therebetween, wherein forming said plurality of storage elements comprises:
- forming a first electrode layer, the first electrode layer comprising or over the storage line;
- forming a storage layer over the first electrode layer, the storage layer comprising the storage material;
- forming a second electrode layer, the second electrode layer over the storage layer;
- and
- removing portions of the first electrode layer, the storage layer, and the second electrode layer;
- and
- forming a plurality of source lines over the storage elements, wherein the source lines extend in a second direction substantially orthogonal to the first direction, and individual ones of the source lines are coupled to corresponding ones of the storage elements.
Dependencies are inferred from the claim text.