Memory device and method for forming the same

A method, comprising:

• forming a bottom dielectric layer over a substrate and a semiconductor layer over the bottom dielectric layer, wherein the semiconductor layer is a polysilicon layer;
• etching the semiconductor layer to a nanowire;
• etching the bottom dielectric layer such that the nanowire is suspended over the substrate;
• performing a first deposition process to form a first ferroelectric layer wrapping around the nanowire, wherein the first ferroelectric layer has a first thickness;
• performing a second deposition process to form a first dielectric layer over the first ferroelectric layer and wrapping around the nanowire;
• performing a third deposition process to form a second ferroelectric layer over the first dielectric layer and wrapping around the nanowire, wherein the second ferroelectric layer has a second thickness less than or equal to the first thickness of the first ferroelectric layer;
• and
• forming a gate metal layer over the second ferroelectric layer.

A memory device, comprising:

• a substrate;
• a semiconductor layer over the substrate, wherein the semiconductor layer is a polysilicon layer, and wherein the semiconductor layer comprises a channel region and source/drain regions on opposite sides of the channel region;
• a gate structure comprising a ferroelectric stack over the channel region of the semiconductor layer and a gate metal over the ferroelectric stack, wherein the ferroelectric stack comprises:
• a first ferroelectric layer;
• a dielectric layer over the first ferroelectric layer;
• and
• a second ferroelectric layer over the dielectric layer, wherein a thickness of the first ferroelectric layer is greater than a thickness of the second ferroelectric layer;
• and
• an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the ILD layer has a portion vertically between a bottom surface of the gate structure and a top surface of the substrate.