Semiconductor structure, method for manufacturing semiconductor structure, memory and method for manufacturing memory

A method for manufacturing a memory, comprising:

• forming a plurality of first storage cells, wherein the plurality of first storage cells are arranged in an array in a first direction and a second direction;
• forming a first transistor array on the plurality of first storage cells, wherein a transistor in the first transistor array is manufactured by a method for manufacturing a transistor, the method for manufacturing a transistor comprises:
• forming a channel, wherein the channel comprises a first material layer and a second material layer surrounding the first material layer, a resistivity of the first material layer is greater than a first preset value, a resistivity of the second material layer is less than a second preset value, and the first preset value is greater than the second preset value;
• forming a gate of the transistor covering at least one side surface of the channel;
• and forming a source and a drain of the transistor at two ends of an extension direction of the channel, respectively;
• wherein, gates of the transistors in each row along the first direction in the first transistor array are physical connected with each other, the physically connected gates forming a first word line, and each of the first storage cells is connected with a source or drain of one transistor in the first transistor array, and both the first direction and the second direction are perpendicular to the extension direction of the channels of the transistors;
• and
• forming, on the first transistor array, a plurality of first bit lines arranged in parallel in the second direction, wherein each of the first bit lines is connected with drains or sources of the transistors in one of rows arranged along the second direction in the transistor array;
• wherein forming the channel comprises;
• providing a first dielectric layer;
• forming a first hole in the first dielectric layer;
• forming the second material layer at a sidewall and a bottom of the first hole;
• and
• filling the first hole with the second material layer to form the first material layer;
• wherein forming the second material layer at the sidewall and the bottom of the first hole comprises:
• forming the second material layer in an oxygen-free atmosphere by an atomic layer deposition process;
• and
• filling the first hole with the second material layer to form the first material layer comprises:
• forming the first material layer in an oxygen-containing atmosphere by in-situ deposition.

A method for manufacturing a semiconductor structure comprising at least one transistor, wherein the method comprises a method for manufacturing the transistor, the method for manufacturing the transistor comprises:

• forming a channel, wherein the channel comprises a first material layer and a second material layer surrounding the first material layer, a resistivity of the first material layer is greater than a first preset value, a resistivity of the second material layer is less than a second preset value, and the first preset value is greater than the second preset value;
• forming a gate of the transistor covering at least one side surface of the channel;
• and
• forming a source and a drain of the transistor at two ends of an extension direction of the channel, respectively;
• wherein forming the channel comprises:
• providing a first dielectric layer;
• forming a first hole in the first dielectric layer;
• forming the second material layer at a sidewall and a bottom of the first hole;
• and
• filling the first hole with the second material layer to form the first material layer;
• wherein after forming the first material layer, the method further comprises:
• etching the first dielectric layer partially to expose the second material layer;
• forming a gate oxide layer on the exposed second material layer;
• and
• filling sequentially with a first conductive material and a second dielectric layer, etching the first conductive material and the second dielectric layer to form a groove, and filling the groove with an insulating material to form a gate isolation structure.