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US 12,609,715 B2Granted
Performing cyclic redundancy checks using parallel computing architectures
AssigneeNVIDIA Corporation
InventorAndrea Miele
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.
Claims20
A system, comprising:
- one or more processors;
- and
- memory including instructions executable by the one or more processors that cause the system to at least:
- allocate two or more portions of one or more transmitted data sequences and one or more cyclic redundancy sequences to two or more threads of a graphics processor;
- and
- use the two or more threads of the graphics processor to perform error detection of the one or more transmitted data sequences at least partially in parallel with the one or more cyclic redundancy sequences to generate one or more cyclic redundancy check values for the one or more transmitted data sequences.
3 more elements
One or more processors, comprising circuitry to:
- allocate two or more portions of one or more transmitted data sequences and one or more cyclic redundancy sequences to two or more threads of a graphics processor;
- and
- use the two or more threads of the graphics processor to perform error detection of the one or more transmitted data sequences at least partially in parallel with the one or more cyclic redundancy sequences to generate one or more cyclic redundancy check values for the one or more transmitted data sequences.
A method, comprising:
- allocating two or more portions of one or more transmitted data sequences and one or more cyclic redundancy sequences to two or more threads of a graphics processor;
- and
- using the two or more threads of the graphics processor to perform error detection of the one or more transmitted data sequences at least partially in parallel with the one or more cyclic redundancy sequences to generate one or more cyclic redundancy check values for the one or more transmitted data sequences.
Dependencies are inferred from the claim text.