Voltage level down-shifting circuit structure with input stage pull-down capacitor

A structure comprising:

• a voltage level down-shifting circuit with a total of four dual-gated transistors,
• wherein the voltage level down-shifting circuit is connected to receive a voltage input signal at a single input node and operable to output an output voltage signal at a single output node,
• wherein the voltage input signal switches between a first voltage and ground and the output voltage signal switches between a second voltage that is less than the first voltage and ground,
• wherein the voltage level down-shifting circuit includes a single input stage including:
• a first transistor having a first front gate;
• a second transistor having a second front gate, wherein the first transistor and the second transistor are connected in series;
• an intermediate node between the first transistor and the second transistor;
• the single input node further connected to the second front gate;
• and
• a capacitor connected to the single input node and to the intermediate node, wherein the capacitor pulls down an intermediate voltage signal on the intermediate node from the second voltage to ground when the input voltage signal switches to ground,
• wherein the voltage level down-shifting circuit further includes an output stage including an inverter connected to the intermediate node and the single output node, and
• wherein the single output node is connected to the first front gate.

A structure comprising:

• a voltage level down-shifting circuit with a total of four dual-gated transistors,
• wherein the voltage level down-shifting circuit is connected to receive a voltage input signal at a single input node and operable to output an output voltage signal at a single output node,
• wherein the voltage input signal switches between a first positive voltage and ground and the output voltage signal switches between a second positive voltage that is less than the first positive voltage and ground,
• wherein the voltage level down-shifting circuit includes a single input stage including:
• a first N-type field effect transistor (NFET) having a first front gate;
• a second NFET having a second front gate, wherein the first NFET and the second NFET are connected in series between a ground rail and a positive supply voltage rail;
• an intermediate node between the first NFET and the second NFET;
• the single input node further connected to the second front gate;
• and
• a capacitor connected to the single input node and the intermediate node, wherein the capacitor pulls down an intermediate voltage signal on the intermediate node from the second positive voltage to ground when the input voltage signal switches to ground,
• wherein the voltage level down-shifting circuit further includes an output stage including an inverter,
• wherein the inverter includes:
• a third NFET having a third front gate connected to the intermediate node;
• a P-type field effect transistor (PFET) having a fourth front gate connected to the intermediate node, wherein the third NFET and the PFET are connected in series between the ground rail and the positive supply voltage rail;
• and
• the single output node between the third NFET and the PFET, and
• wherein the single output node is further connected to the first front gate.