Semiconductor integrated circuit including MOS switch
AssigneeRohm Co., Ltd.
InventorKoichi Takanashi
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor integrated circuit including a metal-oxide-semiconductor (MOS) switch, in which the MOS switch includes a first main MOS transistor having a first polarity, a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor, and a switch control circuit that supplies a first voltage according to a control signal to a gate of the first main MOS transistor, supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor, and is configured to be capable of adjusting a slew rate of each of the first voltage and the second voltage.
Claims12
A semiconductor integrated circuit comprising:
- a metal-oxide-semiconductor (MOS) switch, wherein the MOS switch includes
- a first main MOS transistor having a first polarity,
- a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor,
- a second dummy MOS transistor having the first polarity and having opposed ends each connected to a second end of the first main MOS transistor, and
- a switch control circuit that
- supplies a first voltage according to a control signal to a gate of the first main MOS transistor,
- supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor,
- supplies the second voltage to a gate of the second dummy MOS transistor, and
- is configured to adjust a slew rate of each of the first voltage and the second voltage.
A semiconductor integrated circuit comprising:
- a metal-oxide-semiconductor (MOS) switch, wherein the MOS switch includes
- a first main MOS transistor having a first polarity,
- a second main MOS transistor having a second polarity and connected in parallel with the first main MOS transistor,
- a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor,
- a second dummy MOS transistor having the second polarity and having opposed ends each connected to a second end of the first main MOS transistor,
- a third dummy MOS transistor having the second polarity and connected in parallel with the first dummy MOS transistor,
- a fourth dummy MOS transistor having the second polarity and connected in parallel with the second dummy MOS transistor, and
- a switch control circuit that
- supplies a first voltage according to a control signal to a gate of the first main MOS transistor,
- supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor,
- supplies the second voltage to a gate of the second main MOS transistor,
- supplies the first voltage to a gate of the third dummy MOS transistor,
- supplies the second voltage to a gate of the second dummy MOS transistor,
- supplies the first voltage to a gate of the fourth dummy MOS transistor, and
- is configured to adjust a slew rate of each of the first voltage and the second voltage.
A semiconductor integrated circuit comprising:
- a metal-oxide-semiconductor (MOS) switch, wherein the MOS switch includes
- a first main MOS transistor having a first polarity,
- a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor,
- a second main MOS transistor having a second polarity and connected in parallel with the first main MOS transistor,
- a second dummy MOS transistor having the second polarity and having opposed ends each connected to a second end of the first main MOS transistor,
- a third dummy MOS transistor having the second polarity and connected in parallel with the first dummy MOS transistor,
- a fourth dummy MOS transistor having the second polarity and connected in parallel with the second dummy MOS transistor, and
- a switch control circuit that
- supplies a first voltage according to a control signal to a gate of the first main MOS transistor,
- supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor,
- supplies a third voltage in phase with the second voltage to a gate of the second main MOS transistor,
- supplies a fourth voltage in phase with the first voltage to a gate of the third dummy MOS transistor,
- supplies the second voltage to a gate of the second dummy MOS transistor,
- supplies the fourth voltage to a gate of the fourth dummy MOS transistor, and
- is configured to adjust a slew rate of each of the first voltage, the second voltage, the third voltage, and the fourth voltage.
Dependencies are inferred from the claim text.