Capacitor device and method for manufacturing the same
AssigneeAP Memory Technology Corp.
InventorsWen-Liang Chen, Yen-Jun Li
Life of this patent
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Abstract
A capacitor device is provided. The capacitor device includes a capacitor structure, a conductive line, an interlayer dielectric (ILD) and a first via conductor. The capacitor structure includes a lower electrode and an upper electrode. The conductive line is leveled with the lower electrode and electrically isolated from the lower electrode. The ILD is disposed over the capacitor structure and the conductive line. The first via conductor is adjacent to the capacitor structure and electrically coupled to the conductive line. A method for manufacturing a capacitor die is also provided.
Claims20
A capacitor device, comprising:
- a capacitor structure, comprising a lower electrode and an upper electrode;
- a conductive line leveled with the lower electrode and electrically isolated from the lower electrode;
- an interlayer dielectric (ILD) disposed over the capacitor structure and the conductive line;
- a first via conductor adjacent to the capacitor structure and electrically coupled on an upper surface of the conductive line;
- a third via conductor disposed over the upper electrode of the capacitor structure and electrically coupled to the capacitor structure;
- and
- a top metal layer disposed over the first via conductor and the third via conductor, the top metal layer comprising:
- a first metal line electrically connected to the first via conductor;
- and
- a second metal line electrically connected to the third via conductor,
- wherein a top surface of the first metal line is entirely covered by the ILD, and a top surface of the second metal line is free from being entirely covered by the ILD.
An integrated capacitor device, comprising:
- a capacitor structure, comprising a lower electrode and an upper electrode;
- an interlayer dielectric (ILD) disposed over the capacitor structure;
- a first via conductor electrically connected to the lower electrode, and electrically connected to a first metal line over the first via conductor;
- and
- a second via conductor adjacent to the first via conductor and electrically isolated from the first via conductor, wherein the second via conductor is configured to be a seal ring structure to encircle the capacitor structure and the first via conductor, the second via conductor is electrically connected to a second metal line over the second via conductor, the second metal line and the first metal line are located in the same metal layer,
- wherein a top surface of the second metal line is entirely covered by the ILD, and a top surface of the first metal line is free from being entirely covered by the ILD.
A method for manufacturing an integrated capacitor device, the method comprising:
- receiving a capacitor wafer having a capacitor structure and a conductive line surrounding the capacitor structure, wherein the capacitor structure comprises a lower electrode and an upper electrode, and wherein the conductive line is leveled with the lower electrode and electrically isolated from the lower electrode;
- forming a first via conductor on the conductive line and laterally surrounding the capacitor structure;
- forming a third via conductor on the upper electrode of the capacitor structure;
- forming a metal layer over the first via conductor and the third via conductor to form a first metal line over the first via conductor and a second metal line over the third via conductor;
- forming a passivation layer over the metal layer;
- and
- forming an opening over the second metal line to expose the second metal line from the passivation layer, and the first metal line is entirely covered by the passivation layer.
Dependencies are inferred from the claim text.