Semiconductor memory device and control method of the same

A semiconductor memory device, comprising:

• a memory cell array, including a first subarray and a second subarray arranged apart from the first subarray in a column direction, each of the first subarray and the second subarray including a plurality of word lines, a plurality of bit lines, at least one spare bit line for replacing at least one defective bit line, and a plurality of memory cells connected to the word lines, and the bit lines or the at least one spare bit line;
• and
• a control circuit, coupled to the memory cell array, and configured to activate one of the plurality of word lines in the first subarray and a corresponding one of the plurality of word lines in the second subarray when receives a read command for reading the one of the plurality of word lines in the first subarray;
• wherein in the first subarray when the number of the defective bit lines is higher than the number of the at least one spare bit line, the control circuit is configured to access the memory cells connected to the activated corresponding one of the plurality of word lines in the second subarray instead of the first subarray;
• wherein the control circuit further comprises:
• a first signal generating circuit, configured to generate a first control signal when the at least one defective bit line in the first subarray is selected, for selecting the first subarray or the second subarray as an access object, according to first information corresponding to the selected defective bit line that indicates whether to access the second subarray to replace the first subarray.