Methods of testing repair circuits of memory devices

A method of testing a repair circuit of a memory device, the method comprising:

• presetting first addresses to a first register and a second register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses;
• providing test addresses to the second register, wherein the test addresses are provided from a test host and are addresses configured to cause repair enable signals output from the repair circuit to toggle;
• outputting hit signals by comparing bit values of the first addresses stored in the first register with bit values of the test addresses stored in the second register;
• outputting the repair enable signals based on the hit signals;
• providing, by the test host, a hit signal pattern causing toggling of the repair enable signals to lines carrying the hit signals, and
• determining a status of a path where the repair enable signals are generated based on the toggling of the repair enable signals.

A memory device comprising:

• a memory cell array including memory banks, wherein each of the memory banks includes a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and redundancy memory cells for repairing faulty memory cells among the plurality of memory cells;
• and
• for each of the memory banks, a repair circuit configured to include a plurality of unit circuits configured to generate repair enable signals that instruct a repair operation on the faulty memory cells,
• wherein the unit circuits of the repair circuit comprise:
• fail address memory including a first register and a second register, the first register configured to store first addresses and the second register configured to store test addresses, wherein the test addresses are provided from a test host;
• a comparison circuit configured to output hit signals by comparing bit values of the first addresses stored in the first register with bit values of the test addresses stored the second register;
• and
• a combinational logic circuit configured to output the repair enable signals based on the hit signals,
• wherein a status of a path where the repair enable signals are generated is determined based on logic levels of the repair enable signals, and
• wherein the determining the status of the path where the repair enable signals are generated based on the logic levels of the repair enable signals comprises:
• determining the status of the path as a fail when the first addresses match the test addresses and the repair enable signals have a first logic level;
• or
• determining the status of the path as a fail when the first addresses do not match the test addresses and the repair enable signals have a second logic level that is different than the first logic level.