Test circuit and semiconductor memory system including the test circuit

A semiconductor memory system comprising:

• a memory device comprising a plurality of memory cells that are coupled to a plurality of word lines, wherein the plurality of memory cells are divided into a plurality of first unit areas and each of the plurality of first unit areas is divided into a plurality of second unit areas;
• and
• a test circuit that is coupled to at least one of the plurality of first unit areas,
• wherein the test circuit is configured to:
• set a charging current quantity as a first value and perform charging and discharging on a test node during a first measurement interval;
• change the charging current quantity from the first value to a second value and perform the charging and discharging on the test node during a second measurement interval;
• generate a first counting value and a second counting value by counting the first measurement interval and the second measurement interval;
• generate results of an operation of the first counting value and the second counting value as operation results;
• and
• output at least one of the first counting value, the second counting value, and the operation results as test result information.