Non-volatile memory with intelligent erase testing to avoid neighbor plane disturb
AssigneeSanDisk Technologies LLC
InventorsLiang Li, Dandan Yi, Dana Lee
Life of this patent
Estimating the term…
Abstract
A non-volatile memory system is configured to perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes. Based on that multiplane erase process, the memory system determines that a first group of memory cells in a first plane of the multiple planes is slow to erase. As a result, the system will perform one or more multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase process(es).
Claims20
A non-volatile storage apparatus, comprising:
- multiple planes, each plane comprises multiple blocks of non-volatile memory cells;
- and
- a control circuit connected to the multiple planes, the control circuit is configured to:
- perform multiplane erase for a set of blocks of non-volatile memory cells in multiple planes by applying one or more doses of an erase voltage to the set of blocks of non-volatile memory cells in multiple planes;
- after applying a first dose of the erase voltage to the set of blocks of non-volatile memory cells in multiple planes, determine whether one or more blocks of the set of blocks are slow to erase;
- identify a first block of the set of blocks of non-volatile memory cells in multiple planes that is slowest to erase among the set of blocks of non-volatile memory cells in multiple planes;
- and
- perform multiplane erase for the set of blocks without erasing the first block as part of the multiplane erase.
A non-volatile storage apparatus, comprising:
- non-volatile memory cells arranged in multiple planes;
- and
- a control circuit connected to the memory cells, the control circuit is configured to:
- perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes;
- identify a first group of memory cells in a first plane of the multiple planes that is slowest to erase among the groups of memory cells in multiple planes;
- and
- after the identifying of the first group, perform a multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase processes.
A method of erasing non-volatile storage, comprising:
- performing multiplane erase for a set of blocks of non-volatile memory cells in multiple planes by applying one or more doses of an erase voltage to the set of blocks of non-volatile memory cells in multiple planes;
- after applying a first dose of the erase voltage to the set of blocks in multiple planes, determining that one or more of the set of blocks are slow to erase;
- identifying a first block that is slowest to erase among the set of blocks in multiple planes;
- and
- performing multiplane erase for the set of blocks in multiple planes without erasing the first block as part of the multiplane erase.
Dependencies are inferred from the claim text.