US 12,609,167 B2Granted

Memory, methods of operating memory, systems and storage mediums

AssigneeYangtze Memory Technologies Co., Ltd.

InventorYan Wang

Life of this patent

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Abstract

This application provides a memory including a peripheral circuit and a memory cell array. The peripheral circuit includes a page buffer including a first bit line connection point, a second bit line connection point, a first switching component and a second switching component. The first bit line connection point and the second bit line connection point are connected to a power terminal via independent precharge circuits respectively, and the first bit line connection point and the second bit line connection point are connected to a latch in the page buffer respectively; the precharge circuit is a circuit for precharging the bit lines by the page buffer; the first switching component connects the first bit line connection point and the second bit line connection point; and the second switching component is located on the precharge circuit corresponding to the second bit line connection point.

Claims20

Dependent claims

A memory comprising:

a memory cell array;
and
a peripheral circuit comprising:
a plurality of page buffers, wherein each of the plurality of page buffers comprises a first bit line connection point, a second bit line connection point, a first switching component, and a second switching component;
and
a logic control circuit coupled to the plurality of page buffers and configured to control the plurality of page buffers, wherein
the first bit line connection point and the second bit line connection point are to connect bit lines in the memory cell array, the first bit line connection point and the second bit line connection point are connected to a power terminal via independent precharge circuits, respectively, wherein the first bit line connection point and the second bit line connection point are connected to a latch in each page buffer of the plurality of page buffers, respectively, and a precharge circuit of the independent precharge circuits is a circuit for precharging the bit lines by the page buffer;
the first switching component connects the first bit line connection point and the second bit line connection point;
and
the second switching component is located on the precharge circuit corresponding to the second bit line connection point.

7 more elements

A method of operating a memory, wherein the method is performed by a control logic circuit in a peripheral logic circuit of the memory, the memory comprising:

a memory cell array;
and
the peripheral logic circuit comprising:
a plurality of page buffers, wherein each of the plurality of page buffers comprises a first bit line connection point, a second bit line connection point, a first switching component, and a second switching component;
and
a logic control circuit coupled to the plurality of page buffers and configured to control the plurality of page buffers, wherein
the first bit line connection point and the second bit line connection point are to connect bit lines in the memory cell array, the first bit line connection point and the second bit line connection point are connected to a power terminal via independent precharge circuits, respectively, wherein the first bit line connection point and the second bit line connection point are connected to a latch in each page buffer of the plurality of page buffers, respectively, and a precharge circuit of the independent precharge circuits is a circuit for precharging the bit lines by the page buffer;
the first switching component connects the first bit line connection point and the second bit line connection point;
and
the second switching component is located on the precharge circuit corresponding to the second bit line connection point;
and
the method comprising:
turning off the first switching component and turning on the second switching component when a program operation is performed through the page buffer;
and
turning on the first switching component and turning off the second switching component when a read operation is performed through the page buffer.

12 more elements

A memory system comprising:

one or more memories, each of the memories comprises:
a memory cell array;
and
a peripheral circuit comprising:
a plurality of page buffers, wherein each of the plurality of page buffers comprises a first bit line connection point, a second bit line connection point, a first switching component, and a second switching component;
and
a logic control circuit coupled to the plurality of page buffers and configured to control the plurality of page buffers, wherein
the first bit line connection point and the second bit line connection point are to connect bit lines in the memory cell array, the first bit line connection point and the second bit line connection point are connected to a power terminal via independent precharge circuits, respectively, wherein the first bit line connection point and the second bit line connection point are connected to a latch in each page buffer of the plurality of page buffers, respectively, and a precharge circuit of the independent precharge circuits is a circuit for precharging the bit lines by the page buffer;
the first switching component connects the first bit line connection point and the second bit line connection point;
and
the second switching component is located on the precharge circuit corresponding to the second bit line connection point;
and
a controller coupled to the memories and configured to control the memories.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/542,258Filed 15 Dec 2023
Priority: CN 202311153232.66 Sep 2023
Published: US 2025/0078934 A16 Mar 2025
Granted: 21 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/12
Programming or data input circuits: programming voltage switching circuits