Memory, operation method of memory and memory system including read calibration circuit
AssigneeYangtze Memory Technologies Co., Ltd.
InventorChong Jin
Life of this patent
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Abstract
A memory includes a page buffer that includes a sensing latch circuit, a first charge circuit and a read calibration circuit. The first charge circuit and the sensing latch circuit are coupled to a sensing node, and the read calibration circuit is coupled to the sensing latch circuit at a first end and to the sensing node at a second end, and is configured to calibrate a potential of the sensing node during sensing. The above-mentioned memory is applied in a calibration process of the potential of the sensing node during sensing.
Claims18
A memory, comprising:
- a page buffer comprising:
- a sensing latch circuit;
- a first charge circuit coupled to a sensing node;
- and
- a read calibration circuit, a first end of the read calibration circuit being coupled to the sensing latch circuit and a second end of the read calibration circuit being coupled to the sensing node, and the read calibration circuit being configured to calibrate a potential of the sensing node in a sensing process, wherein:
- the sensing process comprises a calibration stage;
- and
- the read calibration circuit comprises:
- a first sub-circuit configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration stage;
- and
- a second sub-circuit configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage.
An operation method of a memory, comprising:
- discharging a sensing node from a first voltage value to a second voltage value in a first sub-stage of a calibration stage;
- charging the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage;
- and
- storing a state of a memory cell coupled with a bit line in a sensing stage.
A memory system, comprising:
- one or more memories comprising:
- a page buffer comprising:
- a sensing latch circuit;
- a first charge circuit coupled to a sensing node;
- and
- a read calibration circuit, a first end of the read calibration circuit being coupled to the sensing latch circuit and a second end of the read calibration circuit being coupled to the sensing node, and the read calibration circuit being configured to calibrate a potential of the sensing node in a sensing process,
- wherein:
- the sensing process comprises a calibration stage;
- and
- the read calibration circuit comprises:
- a first sub-circuit configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration stage;
- and
- a second sub-circuit configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage;
- and
- a memory controller coupled to the memories and configured to control the memories.
Dependencies are inferred from the claim text.