Managing program disturb in memory devices
AssigneeYangtze Memory Technologies Co., Ltd.
InventorKaikai You
Life of this patent
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Abstract
Example memory devices, memory systems, and methods for reducing program disturb in NAND flash memory are disclosed. One example method includes applying, at a first time and during a channel preparation period of a program operation of a first memory cell in a memory cell array, a first voltage to a first word line coupled to the first memory cell. A second voltage is applied to the first word line at a second time after the first time and during the channel preparation period, where the second voltage is lower than the first voltage. A programming voltage is applied to the first word line after the channel preparation period and during the program operation of the first memory cell.
Claims20
A memory device, comprising:
- a memory cell array comprising memory cells;
- and
- a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
- applying, at a first time and during a channel preparation period of a program operation of a first memory cell in the memory cell array, a first voltage to a first word line coupled to the first memory cell;
- applying, at a second time after the first time and during the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage;
- applying a third voltage to the first word line before the first time, wherein the third voltage is lower than the first voltage;
- applying, at the first time, an eighth voltage to a source line of the memory cell array, wherein the eighth voltage is equal to the third voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell.
A memory system, comprising:
- a memory device, comprising:
- a memory cell array comprising memory cells;
- and
- a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
- applying, at a first time and during a channel preparation period of a program operation of a first memory cell in the memory cell array, a first voltage to a first word line coupled to the first memory cell;
- applying, at a second time after the first time and during the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage;
- applying a third voltage to the first word line before the first time, wherein the third voltage is lower than the first voltage;
- applying, at the first time, an eighth voltage to a source line of the memory cell array, wherein the eighth voltage is equal to the third voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell;
- and
- a controller coupled to the memory device and configured to send a signal to the memory device to initiate the program operation.
A method, comprising:
- applying, at a first time and during a channel preparation period of a program operation of a first memory cell in a memory cell array, a first voltage to a first word line coupled to the first memory cell;
- applying, at a second time after the first time and during the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage;
- applying a third voltage to the first word line before the first time, wherein the third voltage is lower than the first voltage;
- applying, at the first time, an eighth voltage to a source line of the memory cell array, wherein the eighth voltage is equal to the third voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell.
Dependencies are inferred from the claim text.