Memory device and operation method thereof

A memory system, comprising:

• a memory device, comprising:
• a memory cell array comprising a first memory string and a second memory string, wherein the first memory string comprises a first select gate transistor, a plurality of memory cells, and a source select gate transistor, the plurality of memory cells are positioned between the first select gate transistor and the source select gate transistor, and the source select gate transistor is coupled to a source line of the memory cell array;
• and
• a peripheral circuit coupled to the memory cell array and configured to perform a program operation of a first memory cell in the first memory string, wherein the peripheral circuit is configured to:
• apply, at a first time during a channel pre-charge phase of the program operation, a first voltage to a first select line coupled to the first select gate transistor to turn on the first select gate transistor;
• apply, at a second time during a channel boost phase of the program operation after the channel pre-charge phase, a second voltage to the first select line coupled to the first select gate transistor, wherein the second time is after the first time, and the second voltage is larger than the first voltage;
• and
• maintain, from the first time to the second time, a ground reference voltage at a second select line coupled to a second select gate transistor in the second memory string to turn off the second select gate transistor;
• and
• a controller coupled to the memory device and configured to send a signal to the memory device to initiate the program operation.

A method of performing a program operation by a memory device, the method comprising:

• applying, at a first time during a channel pre-charge phase of the program operation, a first voltage to a first select line coupled to a first select gate transistor to turn on the first select gate transistor, wherein the memory device comprises a memory cell array, the memory cell array comprises a first memory string and a second memory string, the first memory string comprises the first select gate transistor, a plurality of memory cells, and a source select gate transistor, the plurality of memory cells are positioned between the first select gate transistor and the source select gate transistor, and the source select gate transistor is coupled to a source line of the memory cell array;
• applying, at a second time during a channel boost phase of the program operation after the channel pre-charge phase, a second voltage to the first select line coupled to the first select gate transistor, wherein the second time is after the first time, and the second voltage is larger than the first voltage;
• and
• maintaining, from the first time to the second time, a ground reference voltage at a second select line coupled to a second select gate transistor in the second memory string to turn off the second select gate transistor.