Memory device and method for calibrating impedance of input-output circuit thereof

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• an input/output circuit configured to transmit data received from an outside through a data pad to the memory cell array or transmit data read from the memory cell array to the outside;
• and
• an impedance calibration circuit configured to generate an impedance calibration code applied to the input/output circuit,
• wherein the impedance calibration circuit is configured to:
• perform a first sub-impedance calibration corresponding to a first impedance mode in a first sub-impedance calibration section, wherein the first impedance mode corresponds to a read operation;
• and
• in response to detecting a change from the first impedance mode to a second impedance mode, perform a second sub-impedance calibration corresponding to the second impedance mode in a second sub-impedance calibration section, wherein the second impedance mode corresponds to a non-target read operation.

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• an input/output circuit configured to transmit data received from an outside through a data pad to the memory cell array or transmit data read from the memory cell array to the outside;
• and
• an impedance calibration circuit configured to generate an impedance calibration code applied to the input/output circuit,
• wherein the impedance calibration circuit is configured to:
• perform a first sub-impedance calibration corresponding to a first impedance mode in a first sub-impedance calibration section, wherein the first impedance mode corresponds to a write operation;
• and
• in response to detecting a change from the first impedance mode to a second impedance mode, perform a second sub-impedance calibration corresponding to the second impedance mode in a second sub-impedance calibration section, wherein the second impedance mode corresponds to a non-target read operation.