DDR PHY critical clock switching and gating architecture
AssigneeQUALCOMM Incorporated
InventorsYong Xu, Boris Dimitrov Andreev, Yuxin Li, Vikas Mahendiyan
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Abstract
In certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an OR gate having a first input, a second input, and an output, wherein the output of the OR gate is coupled to the clock path. The system also includes a first clock gating circuit coupled between the first clock source and the first input of the OR gate, and a second clock gating circuit coupled between the second clock source and the second input of the OR gate.
Claims18
A system, comprising:
- a first clock source configured to generate a first clock signal;
- a second clock source configured to generate a second clock signal;
- a third clock source configured to generate a third clock signal;
- a first OR gate having a first input, a second input, and an output;
- a first clock gating circuit coupled between the first clock source and the first input of the first OR gate;
- a second clock gating circuit coupled between the third clock source and the second input of the first OR gate;
- a second OR gate having a first input, a second input, and an output;
- a third clock gating circuit coupled between the second clock source and the first input of the second OR gate;
- a fourth clock gating circuit coupled between the third clock source and the second input of the second OR gate;
- a multiplexer having a first input, a second input, and an output;
- a first clock path coupled between the output of the first OR gate and the first input of the multiplexer;
- and
- a second clock path coupled between the output of the second OR gate and the second input of the multiplexer.
A system, comprising:
- a first OR gate having a first input, a second input, and an output;
- a first clock gating circuit coupled the first input of the first OR gate;
- a second clock gating circuit coupled to the second input of the first OR gate;
- a second OR gate having a first input, a second input, and an output;
- a third clock gating circuit coupled to the first input of the second OR gate;
- a fourth clock gating circuit coupled to the second input of the second OR gate;
- a first multiplexer having a first input, a second input, and an output;
- a first clock path coupled between the output of the first OR gate and the first input of the first multiplexer;
- a second clock path coupled between the output of the second OR gate and the second input of the first multiplexer;
- a delay circuit coupled to the output of the first multiplexer;
- a second multiplexer having a first input, a second input, and an output, wherein the output of the second multiplexer is coupled to a control input of the delay circuit;
- a first delay control circuit coupled between the first clock path and the first input of the second multiplexer;
- and
- a second delay control circuit coupled between the second clock path and the second input of the second multiplexer.
Dependencies are inferred from the claim text.