Address mapping for improved reliability
AssigneeRambus Inc.
InventorsSteven C. Woo, Taeksang Song
Life of this patent
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Abstract
The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.
Claims20
A memory module, comprising:
- a command/address interface to receive a first row address;
- a first dynamic random access memory (DRAM) device including a first memory array and first neighbor-refresh control circuitry, the first DRAM device to receive the first row address and to, based on the first row address, access a first row in the first memory array having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address, the first DRAM device to also, based on receiving a neighbor refresh command associated with the first row address, refresh the first neighboring row;
- and
- a second DRAM device including a second memory array and second neighbor-refresh control circuitry, the second DRAM device to receive the first row address and to, based on the first row address, access a second row in the second memory array having a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, the second DRAM device to also, based on receiving the neighbor refresh command associated with the first row address, refresh the second neighboring row, wherein a first address that the first DRAM receives that maps to the first internal neighboring row address and a second address that the second DRAM receives that maps to the second internal neighboring row address are to be not equal.
A dynamic random access memory (DRAM) device, comprising:
- a memory array having a plurality of rows accessed according to a plurality of internal row addresses;
- a command/address interface to receive a plurality of external row addresses;
- and
- externally configurable row address mapping circuitry to, based on a mapping mode indicator, select a one of a plurality of mapping modes, each of the plurality of mapping modes to provide unique, among the plurality of mapping modes, translations of the plurality of external row addresses to corresponding ones of the plurality of internal row addresses;
- and
- neighbor-refresh control circuitry to, based on the selected one of the plurality of mapping modes, provide translations of a plurality of external neighbor row refresh addresses to corresponding ones of the plurality of internal row addresses to be refreshed.
A method of operating a memory module, comprising:
- receiving, via a command/address interface, a first row address;
- receiving, by a first dynamic random access memory (DRAM) device on the memory module that includes a first memory array, the first row address;
- based on the first row address, accessing a first row in the first memory array that has a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address;
- receiving, by the first DRAM device and the second DRAM device, the first row address in association with a first neighbor refresh command;
- based on the first neighbor refresh command and the first row address, refreshing, by the first DRAM device, the first neighboring row;
- receiving, by a second DRAM device on the memory module that includes a second memory array, the first row address;
- and
- based on the first row address, accessing a second row in the second memory array that has a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address where a first external row address received via the command/address interface that maps to the first internal neighboring row address and a second external row address received via the command/address interface that maps to the second internal neighboring row address are not equal;
- and
- based on the first neighbor refresh command and the first row address, refreshing, by the second DRAM device, the second neighboring row.
Dependencies are inferred from the claim text.