Memory cell arrangements and method of operating a memory cell

A memory cell arrangement, comprising:

• a memory cell comprising:
• a field-effect transistor comprising a gate terminal, a first source/drain terminal, and a second source/drain terminal, and
• a spontaneously-polarizable capacitor connected to the first source/drain terminal of the field-effect transistor, the spontaneously-polarizable capacitor having a corresponding capacitance;
• and
• a write modification circuit electrically conductively connected to the second source/drain terminal or the spontaneously-polarizable capacitor, wherein the write modification circuit comprises:
• a plurality of write capacitors, wherein each write capacitor of the plurality of write capacitors has a respective capacitance,
• wherein the write modification circuit is configured to select one or more write capacitors of the plurality of write capacitors to provide an effective write capacitance when the memory cell is written.