Semiconductor circuit

Abstract

A semiconductor circuit according to the present disclosure includes first and second memory cells, first and second signal lines, a sense amplifier, a first switch, and a second switch. The sense amplifier includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit is configured to apply, to a second node, a voltage inverted with respect to a voltage at a first node and apply, to the first node, a voltage inverted with respect to a voltage at the second node. The first transistor includes a source, and includes a gate and a drain that are coupled to the first node. The second transistor includes a source, and includes a gate and a drain that are coupled to the second node. The third transistor includes a source, a gate to which a control voltage is applicable, and a drain coupled to the source of the first transistor, the source of the second transistor, or both. The first switch is configured to couple the first signal line and the first node to each other. The second switch is configured to couple the second signal line and the second node to each other.

Dependencies are inferred from the claim text.