Write leveling circuit applied to memory, method for controlling write leveling circuit and memory

A write leveling circuit applied to a memory, comprising:

• a write signal generation unit configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal, wherein the first indication signal indicates a shortened time of a Column Address Strobe Write Latency (CWL) of the memory and comprises the specified bit, and a character in the specified bit indicates that the shortened time is an odd multiple of a clock cycle of the first clock signal or an even multiple of the clock cycle of the first clock signal;
• a sampling unit which is connected to the write signal generation unit and configured to receive a first Data Strobe Signal (DQS) and the second write signal, and output a second sampling signal according to the first DQS and the second write signal;
• and
• a delay unit configured to delay the received first DQS and output a second DQS;
• wherein the sampling unit is connected to the delay unit, and configured to receive the second DQS outputted by the delay unit and output a first sampling signal according to the second DQS and the second write signal, the first sampling signal characterizing whether an effective edge of the first clock signal is aligned with an effective edge of the first DQS;
• wherein the first sampling signal is configured to instruct to regulate a delay time of the first DQS in response to the first sampling signal characterizing that the effective edge of the first clock signal is not aligned with the effective edge of the first DQS, and the second sampling signal is configured to instruct to regulate a delay time of the first write signal or the delay time of the first DQS in response to the first sampling signal characterizing that the effective edge of the first clock signal is aligned with the effective edge of the first DQS, and the effective edge of the first DQS is not aligned with the effective edge of the second write signal.

A memory comprising a write leveling circuit, wherein the write leveling circuit comprises:

• a write signal generation unit configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal, wherein the first indication signal indicates a shortened time of a Column Address Strobe Write Latency (CWL) of the memory and comprises the specified bit, and a character in the specified bit indicates that the shortened time is an odd multiple of a clock cycle of the first clock signal or an even multiple of the clock cycle of the first clock signal;
• and
• a sampling unit which is connected to the write signal generation unit and configured to receive a first Data Strobe Signal (DQS) and the second write signal, and output a second sampling signal according to the first DQS and the second write signal;
• wherein the first indication signal comprises at least one binary character, the specified bit is a lowest bit of the first indication signal, and the write signal generation unit comprises:
• a preprocessing module configured to sum the first indication signal and the character in the specified bit of the first indication signal, to obtain a preprocessed signal;
• and
• a determination module which is connected to the preprocessing module, and configured to delay the first write signal based on the first clock signal, the preprocessed signal, a second indication signal and the specified bit of the first indication signal, and output the second write signal, wherein the second indication signal indicates the CWL of the memory.