Memory devices and stack memory devices generating data strobing signal for data output
AssigneeSK hynix Inc.
InventorsChang Kwon Lee, Jong Chan Yoon
Life of this patent
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Abstract
A memory device includes a base chip configured to generate a first read flag, a second read flag, and a plurality of alignment data strobing signals, responsive to a clock signal and a control signal, and a memory chip configured to output data stored in a first pseudo channel included in a memory core as pipe data, responsive to the first read flag and the alignment data strobing signals, and output data stored in a second pseudo channel included in the memory core as the pipe data, responsive to the second read flag and the alignment data strobing signals.
Claims18
A memory device comprising:
- a base chip configured to generate a first read flag, a second read flag, and a plurality of alignment data strobing signals, each of which is generated in response to a clock signal and a control signal, wherein the base chip comprises:
- a control signal decoder configured to decode the control signal, based on the clock signal to generate a read command, a first pseudo read command, a second pseudo read command, and an identification signal;
- and
- an alignment control circuit configured to divide the clock signal to generate a data strobing signal, generate the alignment data strobing signals, based on the data strobing signal, and generate the first read flag and the second read flag aligned with the alignment data strobing signals, based on the read command, the first pseudo read command, and the second pseudo read command;
- and
- a memory chip configured to output data stored in a first pseudo channel in a memory core as pipe data, data output from the pseudo channel based on the first read flag and the alignment data strobing signals, the memory chip being additionally configured to output data stored in a second pseudo channel in the memory core as the pipe data, the pipe data stored in the second pseudo channel based on the second read flag and the alignment data strobing signals.
A stack memory device comprising a plurality of memory chips stacked over a base chip, wherein the base chip comprises:
- an operation control circuit configured to:
- generate a first read flag in synchronization with alignment data strobing signals when a read operation on a first pseudo channel is performed, and
- generate a second read flag in synchronization with the alignment data strobing signals when a read operation on a second pseudo channel is performed;
- a control signal decoder configured to:
- decode a control signal, responsive to a clock signal to generate a read command, a first pseudo read command, a second pseudo read command, and an identification signal;
- and
- an alignment control circuit configured to:
- divide the clock signal to generate a data strobing signal,
- generate the alignment data strobing signals, responsive to the data strobing signal, and
- generate the first read flag and the second read flag aligned with the alignment data strobing signals, responsive to the read command, the first pseudo read command, and the second pseudo read command, and
- wherein each of the plurality of memory chips comprises a memory core including the first pseudo channel and the second pseudo channel and is configured to output pipe data, responsive to the alignment data strobing signals, the first read flag, and the second read flag when a read operation on the first pseudo channel or the second pseudo channel is performed.
Dependencies are inferred from the claim text.