US 12,609,145 B2Granted

ZQ calibration circuit and ZQ calibration method

AssigneeSamsung Electronics Co., Ltd.

InventorsBumsoo Lee, Youngtaek Cho

Life of this patent

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Abstract

Provided are a ZQ calibration circuit and a ZQ calibration method. The ZQ calibration circuit includes: a first calibration circuit; and a second calibration circuit sharing a first ZQ voltage with the first calibration circuit, wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor. The first calibration circuit includes: a first comparator; a second comparator; a first pull-up counter; a first pull-up driver; and a first switch electrically interconnecting the first pull-up counter. The second calibration circuit includes: a third comparator; a fourth comparator; a second pull-up counter; a second pull-up driver; and a second switch connected to the second pull-up counter and turned on based on a second logic level of the clock signal to electrically interconnect the second pull-up counter and the second pull-up driver.

Claims20

Dependent claims

A ZQ calibration circuit comprising:

a first calibration circuit;
and
a second calibration circuit sharing a first ZQ voltage with the first calibration circuit,
wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor, and
wherein the first calibration circuit comprises:
a first comparator configured to generate a first counting signal by comparing the first ZQ voltage with a first reference voltage;
a second comparator configured to generate a second counting signal by comparing the first ZQ voltage with a second reference voltage;
a first pull-up counter configured to count a first pull-up code based on the first counting signal, the second counting signal, and a first counting enable signal;
a first pull-up driver configured to pull-up drive the first ZQ voltage based on the first pull-up code;
and
a first switch electrically interconnecting the first pull-up counter and the first pull-up driver by being turned on based on a first logic level of a clock signal, and
wherein the second calibration circuit comprises:
a third comparator configured to generate a third counting signal by comparing the first ZQ voltage with a third reference voltage;
a fourth comparator configured to generate a fourth counting signal by comparing the first ZQ voltage with a fourth reference voltage;
a second pull-up counter configured to count a second pull-up code based on the third counting signal, the fourth counting signal, and a second counting enable signal;
a second pull-up driver configured to pull-up drive the first ZQ voltage based on the second pull-up code;
and
a second switch connected to the second pull-up counter and turned on based on a second logic level of the clock signal to electrically interconnect the second pull-up counter and the second pull-up driver.

15 more elements

A ZQ calibration circuit comprising:

a first calibration circuit;
and
a second calibration circuit,
wherein the first calibration circuit comprises:
a first comparator configured to generate a first counting signal by comparing a first ZQ voltage with a first reference voltage, wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor;
a second comparator configured to generate a second counting signal by comparing the first ZQ voltage with a second reference voltage;
a first pull-up counter configured to count a first pull-up code based on the first counting signal, the second counting signal, and a first counting enable signal;
a first pull-up driver configured to pull-up drive the first ZQ voltage based on the first pull-up code;
a first switch electrically interconnecting the first pull-up counter and the first pull-up driver by being turned on based on a first logic level of a clock signal;
a third comparator configured to generate a third counting signal by comparing a second ZQ voltage, which is different from the first ZQ voltage, with the first reference voltage;
a fourth comparator configured to generate a fourth counting signal by comparing the second ZQ voltage with the second reference voltage;
a first pull-down counter configured to count a first pull-down code based on the third counting signal, the fourth counting signal, and the first counting enable signal;
and
a first pull-down driver configured to pull-down drive the second ZQ voltage based on the first pull-down code.

11 more elements

A ZQ calibration method comprising:

generating a first counting signal by comparing a first ZQ voltage with a first reference voltage, wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor;
generating a second counting signal by comparing the first ZQ voltage with a second reference voltage;
counting a first pull-up code based on the first counting signal, the second counting signal, and a first counting enable signal;
turning on a first switch and turning off a second switch based on a first logic level of a clock signal;
and
pull-up driving the first ZQ voltage based on the first pull-up code.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/386,463Filed 2 Nov 2023
Priority: KR 10-2022-019107730 Dec 2022
Published: US 2024/0221807 A14 Jul 2024
Granted: 21 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/022
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in I/O circuitry
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…