Read operations for a memory array and register
AssigneeMicron Technology, Inc.
InventorVijayakrishna J. Vankayala
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of memory cells configured to store first data, wherein the first data is output from the memory array based at least in part on the memory device receiving a first command;
- a register configured to store second data, wherein the second data is output from the register based at least in part on the memory device receiving a second command, wherein the first command and the second command are during first consecutive clock cycles;
- and
- a multiplexer coupled with the memory array, the register, and a data bus, wherein the multiplexer is configured to output the first data and the second data on the data bus during second consecutive sets of clock cycles.
A method, comprising:
- receiving, during a first set of clock cycles, a first command for reading first data of a memory array of a memory device, wherein the memory device comprises the memory array and a register associated with one or more parameters for operation of the memory device, and wherein the memory device is associated with a first latency between receiving the first command and reading the first data;
- receiving a second command for reading second data of the register of the memory device during a second set of clock cycles, the second set of clock cycles consecutive with the first set of clock cycles, wherein the memory device is associated with a second latency between receiving the second command and reading the second data;
- and
- outputting the first data from the memory array and the second data from the register via a data bus coupled with the memory array and the register based at least in part on receiving the first command and the second command, wherein the first data is output from the memory array during a third set of clock cycles and the second data is output from the register during a fourth set of clock cycles, and wherein a last clock cycle of the third set of clock cycles and a first clock cycle of the fourth set of clock cycles are consecutive clock cycles.
A memory device comprising:
- a memory array comprising a plurality of memory cells configured to store first data, wherein the first data is output from the memory array based at least in part on the memory device receiving a first command;
- a first buffer coupled with the memory array and configured to buffer the first data based at least in part on the first data being output from the memory array, wherein the first buffer comprises a first-in first-out (FIFO) buffer;
- a register configured to store second data, wherein the second data is output from the register based at least in part on the memory device receiving a second command different than the first command;
- a second buffer coupled with the register and configured to buffer the second data based at least in part on the second data being output from the register, the second buffer comprising a FIFO buffer;
- and
- a multiplexer coupled with the first buffer, the second buffer, and a data bus, wherein the multiplexer is configured to output the first data and the second data on the data bus during consecutive sets of clock cycles.
Dependencies are inferred from the claim text.